GICM_CLRSPI_NSR, Clear Non-secure SPI Pending Register

The GICM_CLRSPI_NSR characteristics are:

Purpose

Removes the pending state from a valid SPI if permitted by the Security state of the access and the GICD_NSACR<n> value for that SPI.

A write to this register changes the state of a pending SPI to inactive, and the state of an active and pending SPI to active.

This register is present only when GICM_TYPER.CLR == 1. Otherwise, direct accesses to GICM_CLRSPI_NSR are RES0.

When GICD_CTLR.DS == 1, this register provides functionality for all SPIs.

GICM_CLRSPI_NSR is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																			INTID

Reserved, RES0.

This field is an alias of GICD_CLRSPI_NSR.

Writes to this register have no effect if:

The value written specifies a Secure SPI, the value is written by a Non-secure access, and the value of the corresponding GICD_NSACR<n> register is less than 0b10.
The value written specifies an invalid SPI.
The SPI is not pending.

16-bit accesses to bits [15:0] of this register must be supported.

Note

A Secure access to this register can clear the pending state of any valid SPI.

Component	Frame	Offset	Instance
GIC Distributor	MSI_base	0x0048	GICM_CLRSPI_NSR

Accesses on this interface are WO.

15/03/2024 21:50; 3156453dc257d36c4630671c3d896bfc69048210