CTIDEVARCH, CTI Device Architecture register

The CTIDEVARCH characteristics are:

Purpose

Identifies the programmers' model architecture of the CTI component.

CTIDEVARCH is in the Debug power domain.

If the CTI is CTIv1, this register is OPTIONAL. If the CTI is CTIv2, this register is mandatory.

Arm recommends that the CTI is CTIv2.

In an Armv8.5 compliant implementation, the CTI must be CTIv2.

If this register is not implemented, CTIDEVAFF0 and CTIDEVAFF1 are also not implemented.

CTIDEVARCH is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARCHITECT											PRESENT	REVISION				ARCHID

Defines the architect of the component. For CTI, this is Arm Limited.

Bits [31:28] are the JEP106 continuation code, 0b0100.

Bits [27:21] are the JEP106 identification code, 0b0111011.

Reads as 0b01000111011.

Access to this field is RO.

DEVARCH present. Indicates that the CTIDEVARCH register is present.

Reads as 0b1.

Access to this field is RO.

Revision. Defines the architecture revision of the component.

The value of this field is an IMPLEMENTATION DEFINED choice of:

REVISION	Meaning
0b0000	First revision.
0b0001	As 0b0000, and also adds support for CTIDEVCTL.

All other values are reserved.

When FEAT_DoPD is implemented, the value 0b0000 is not permitted.

Access to this field is RO.

Defines this part to be an Armv8 debug component. For architectures defined by Arm this is further subdivided.

For CTI:

This corresponds to CTI architecture version CTIv2.

Reads as 0x1A14.

Access to this field is RO.

Component	Offset	Instance
CTI	0xFBC	CTIDEVARCH

Accesses to this register are RO.

15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d