The EDCIDR2 characteristics are:
Provides information to identify an external debug component.
For more information, see 'About the Component Identification scheme'.
When FEAT_DoPD is implemented, EDCIDR2 is in the Core power domain. Otherwise, EDCIDR2 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
EDCIDR2 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_2 |
Reserved, RES0.
Preamble.
Reads as 0x05.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
Debug | 0xFF8 | EDCIDR2 |
Accessible as follows:
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
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