EDDFR2, External Debug Feature Register 2

The EDDFR2 characteristics are:

Purpose

Provides top-level information about the debug system in AArch64.

There are no configuration notes.

EDDFR2 is a 64-bit register.

Reserved, RES0.

This field either has the same value as ID_AA64DFR2_EL1.TRBE_EXC or reads as zero.

This field either has the same value as ID_AA64DFR2_EL1.SPE_nVM or reads as zero.

This field either has the same value as ID_AA64DFR2_EL1.SPE_EXC or reads as zero.

Reserved, RES0.

Breakpoints and watchpoint enhancements.

The value of this field is an IMPLEMENTATION DEFINED choice of:

BWE	Meaning
0b0000	This field does not indicate whether DBGBCR<n>_EL1.MASK and address mismatch breakpoints are implemented.
0b0001	DBGBCR<n>_EL1.MASK and address mismatch breakpoints are implemented.
0b0010	As 0b0001, and address mismatch watchpoints are implemented.

All other values are reserved.

FEAT_BWE implements the functionality identified by the value 0b0001.

FEAT_BWE2 implements the functionality identified by the value 0b0010.

When this field is 0b0000, ID_AA64DFR1_EL1.ABLE might indicate the presence of support for DBGBCR<n>_EL1.MASK and address mismatch breakpoints.

From Armv9.5, the value 0b0001 is not permitted.

In an implementation that supports AArch64, this field has the same value as ID_AA64DFR2_EL1.BWE.

Access to this field is RO.

This field either has the same value as ID_AA64DFR2_EL1.STEP or reads as zero.

Component	Offset	Instance
Debug	0xD50	EDDFR2

Accessible as follows:

When IsCorePowered(), !DoubleLockStatus(), and (!IsZero(EDDFR2) or !OSLockStatus()), accesses to this register are RO.
When FEAT_DoPD is implemented and !IsCorePowered(), accesses to this register generate an error response.
Otherwise, accesses to this register are IMPDEF.

15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d