The ERRIIDR characteristics are:
Defines the implementer of the component.
This register is present only when RAS System Architecture v1p1 is implemented. Otherwise, direct accesses to ERRIIDR are RES0.
ERRIIDR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ProductID | Variant | Revision | Implementer |
Part number, bits [11:0]. The part number is selected by the designer of the component.
If ERRPIDR0 and ERRPIDR1 are implemented, ERRPIDR0.PART_0 matches bits [7:0] of ERRIIDR.ProductID and ERRPIDR1.PART_1 matches bits [11:8] of ERRIIDR.ProductID.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Component major revision.
This field distinguishes product variants or major revisions of the product.
If ERRPIDR2 is implemented, ERRPIDR2.REVISION matches ERRIIDR.Variant.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Component minor revision.
This field distinguishes minor revisions of the product.
If ERRPIDR3 is implemented, ERRPIDR3.REVAND matches ERRIIDR.Revision.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Contains the JEP106 manufacturer's identification code of the designer of the RAS component.
The code identifies the designer of the component, which might not be the same as the implementer of the device containing the component.
Zero is not a valid JEP106 identification code, meaning a value of zero for ERRIIDR indicates this register is not implemented.
For an implementation designed by Arm, this field reads as 0x43B.
Bits [11:8] contain the JEP106 bank identifier of the designer minus 1.
Bit 7 is RES0.
Bits [6:0] contain bits [6:0] of the JEP106 manufacturer's identification code of the designer.
If ERRPIDR4 is implemented, ERRPIDR4.DES_2 matches bits [11:8] of this field.
If ERRPIDR2 is implemented, ERRPIDR2.DES_1 matches bits [6:4] of this field.
If ERRPIDR1 is implemented, ERRPIDR1.DES_0 matches bits [3:0] of this field.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Component | Offset |
---|---|
RAS | 0xE10 |
Accesses to this register are RO.
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
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