MPAMCFG_IN_TL, MPAM Ingress PARTID Translation Configuration Register

The MPAMCFG_IN_TL characteristics are:

Purpose

Enables ingress PARTID translation and configures direct ingress PARTID translations.

Configuration

The power domain of MPAMCFG_IN_TL is IMPLEMENTATION DEFINED.

This register is present only when FEAT_MPAM_MSC_DOMAINS is implemented and MPAMF_IDR.HAS_IN_TL == 1. Otherwise, direct accesses to MPAMCFG_IN_TL are RES0.

The power and reset domain of each MSC component is specific to that component.

Attributes

MPAMCFG_IN_TL is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
ENABLERES0PARTID_TL

ENABLE, bit [31]

Enables ingress PARTID translation in the MSC.

ENABLEMeaning
0b0

Ingress PARTID translation is disabled.

0b1

Ingress PARTID translation is enabled.

Bits [30:16]

Reserved, RES0.

PARTID_TL, bits [15:0]
When MPAMF_IN_TL_IDR.HAS_DIRECT_TL == 1:

PARTID to be used as direct translation of the ingress PARTID configured in MPAMCFG_PART_SEL.PARTID_SEL when MPAMCFG_PART_SEL.INGRESS_TL == 1.


Otherwise:

Reserved, RES0.

Accessing MPAMCFG_IN_TL

This register is within the MPAM feature page memory frames.

In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:

MPAMCFG_IN_TL_s, MPAMCFG_IN_TL_ns, MPAMCFG_IN_TL_rt, and MPAMCFG_IN_TL_rl must be separate registers:

When RIS is implemented, loads and stores to MPAMCFG_IN_TL access the ingress PARTID translation configuration settings without being affected by MPAMCFG_PART_SEL.RIS.

MPAMCFG_IN_TL can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_s0x3008MPAMCFG_IN_TL_s

Accesses to this register are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_ns0x3008MPAMCFG_IN_TL_ns

Accesses to this register are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_rt0x3008MPAMCFG_IN_TL_rt

When FEAT_RME is implemented, accesses to this register are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_rl0x3008MPAMCFG_IN_TL_rl

When FEAT_RME is implemented, accesses to this register are RW.


15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d

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