MPAMCFG_IN_TL_BASE, MPAM Ingress PARTID Translation Base Configuration Register

The MPAMCFG_IN_TL_BASE characteristics are:

Purpose

Configures the base value used to compute translation PARTIDs for ingress PARTIDs that do not have direct translation.

Configuration

The power domain of MPAMCFG_IN_TL_BASE is IMPLEMENTATION DEFINED.

This register is present only when FEAT_MPAM_MSC_DOMAINS is implemented, MPAMF_IDR.HAS_IN_TL == 1, and MPAMF_IN_TL_IDR.HAS_BASE_MASK == 1. Otherwise, direct accesses to MPAMCFG_IN_TL_BASE are RES0.

The power and reset domain of each MSC component is specific to that component.

Attributes

MPAMCFG_IN_TL_BASE is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																BASE

Bits [31:16]

Reserved, RES0.

BASE, bits [15:0]

Base value used to compute the ingress translation of PARTIDs that do not have a direct translation configured.

Accessing MPAMCFG_IN_TL_BASE

This register is within the MPAM feature page memory frames.

In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:

MPAMCFG_IN_TL_BASE_s must only be accessible from the Secure MPAM feature page.
MPAMCFG_IN_TL_BASE_ns must only be accessible from the Non-secure MPAM feature page.
MPAMCFG_IN_TL_BASE_rt must only be accessible from the Root MPAM feature page.
MPAMCFG_IN_TL_BASE_rl must only be accessible from the Realm MPAM feature page.

MPAMCFG_IN_TL_BASE_s, MPAMCFG_IN_TL_BASE_ns, MPAMCFG_IN_TL_BASE_rt, and MPAMCFG_IN_TL_BASE_rl must be separate registers:

The Secure instance (MPAMCFG_IN_TL_BASE_s) accesses the ingress PARTID translation base used for Secure PARTIDs.
The Non-secure instance (MPAMCFG_IN_TL_BASE_ns) accesses the ingress PARTID translation base used for Non-secure PARTIDs.
The Root instance (MPAMCFG_IN_TL_BASE_rt) accesses the ingress PARTID translation base used for Root PARTIDs.
The Realm instance (MPAMCFG_IN_TL_BASE_rl) accesses the ingress PARTID translation base used for Realm PARTIDs.

When RIS is implemented, loads and stores to MPAMCFG_IN_TL_BASE access the ingress PARTID translation base configuration settings without being affected by MPAMCFG_PART_SEL.RIS.

MPAMCFG_IN_TL_BASE can be accessed through the memory-mapped interfaces:

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_s	0x3010	MPAMCFG_IN_TL_BASE_s

Accesses to this register are RW.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_ns	0x3010	MPAMCFG_IN_TL_BASE_ns

Accesses to this register are RW.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_rt	0x3010	MPAMCFG_IN_TL_BASE_rt

When FEAT_RME is implemented, accesses to this register are RW.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_rl	0x3010	MPAMCFG_IN_TL_BASE_rl

When FEAT_RME is implemented, accesses to this register are RW.

15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d