The MPAMCFG_OUT_TL characteristics are:
Enables egress PARTID translation and configures direct egress PARTID translations.
The power domain of MPAMCFG_OUT_TL is IMPLEMENTATION DEFINED.
This register is present only when FEAT_MPAM_MSC_DOMAINS is implemented and MPAMF_IDR.HAS_OUT_TL == 1. Otherwise, direct accesses to MPAMCFG_OUT_TL are RES0.
The power and reset domain of each MSC component is specific to that component.
MPAMCFG_OUT_TL is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE | RES0 | PARTID_TL |
Enables egress PARTID translation in the MSC.
ENABLE | Meaning |
---|---|
0b0 |
Egress PARTID translation is disabled. |
0b1 |
Egress PARTID translation is enabled. |
Reserved, RES0.
PARTID to be used as direct translation of the egress PARTID configured in MPAMCFG_PART_SEL.PARTID_SEL when MPAMCFG_PART_SEL.INGRESS_TL == 0.
Reserved, RES0.
This register is within the MPAM feature page memory frames.
In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:
MPAMCFG_OUT_TL_s, MPAMCFG_OUT_TL_ns, MPAMCFG_OUT_TL_rt, and MPAMCFG_OUT_TL_rl must be separate registers:
When RIS is implemented, loads and stores to MPAMCFG_OUT_TL access the egress PARTID translation configuration settings without being affected by MPAMCFG_PART_SEL.RIS.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x3208 | MPAMCFG_OUT_TL_s |
Accesses to this register are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x3208 | MPAMCFG_OUT_TL_ns |
Accesses to this register are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rt | 0x3208 | MPAMCFG_OUT_TL_rt |
When FEAT_RME is implemented, accesses to this register are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rl | 0x3208 | MPAMCFG_OUT_TL_rl |
When FEAT_RME is implemented, accesses to this register are RW.
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
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