Lines Matching refs:a0
282 PTR_SUBU t0,a0,a1
302 move v0,a0
313 xor t8,a1,a0
316 PTR_SUBU a3, zero, a0
324 C_STHI t8,0(a0)
325 PTR_ADDU a0,a0,a3
334 andi t8,a0,7
349 sb a3, 6(a0)
352 sb a3, 5(a0)
355 sb a3, 4(a0)
358 sb a3, 3(a0)
361 sb a3, 2(a0)
364 sb a3, 1(a0)
367 sb a3, 0(a0)
372 PTR_ADDU a0,a0,t8
406 PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */
415 PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */
423 PREFETCH_FOR_STORE (1, a0)
424 PREFETCH_FOR_STORE (2, a0)
425 PREFETCH_FOR_STORE (3, a0)
429 sltu v1,t9,a0
432 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4)
435 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1)
440 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*3)
448 sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */
453 PREFETCH_FOR_STORE (2, a0)
455 PREFETCH_FOR_STORE (4, a0)
456 PREFETCH_FOR_STORE (5, a0)
459 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*5)
476 C_ST t0,UNIT(0)(a0)
477 C_ST t1,UNIT(1)(a0)
478 C_ST REG2,UNIT(2)(a0)
479 C_ST REG3,UNIT(3)(a0)
480 C_ST REG4,UNIT(4)(a0)
481 C_ST REG5,UNIT(5)(a0)
482 C_ST REG6,UNIT(6)(a0)
483 C_ST REG7,UNIT(7)(a0)
496 C_ST t0,UNIT(8)(a0)
497 C_ST t1,UNIT(9)(a0)
498 C_ST REG2,UNIT(10)(a0)
499 C_ST REG3,UNIT(11)(a0)
500 C_ST REG4,UNIT(12)(a0)
501 C_ST REG5,UNIT(13)(a0)
502 C_ST REG6,UNIT(14)(a0)
503 C_ST REG7,UNIT(15)(a0)
504 PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */
505 bne a0,a3,L(loop16w)
530 C_ST t0,UNIT(0)(a0)
531 C_ST t1,UNIT(1)(a0)
532 C_ST REG2,UNIT(2)(a0)
533 C_ST REG3,UNIT(3)(a0)
534 C_ST REG4,UNIT(4)(a0)
535 C_ST REG5,UNIT(5)(a0)
536 C_ST REG6,UNIT(6)(a0)
537 C_ST REG7,UNIT(7)(a0)
538 PTR_ADDIU a0,a0,UNIT(8)
551 PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */
556 PTR_ADDIU a0,a0,UNIT(1)
558 bne a0,a3,L(wordCopy_loop)
559 C_ST REG3,UNIT(-1)(a0)
570 sw REG3,0(a0)
571 PTR_ADDIU a0,a0,4
578 PTR_ADDU a3,a0,a2 /* a3 is the last dst address */
581 PTR_ADDIU a0,a0,1
583 bne a0,a3,L(lastbloop)
584 sb v1,-1(a0)
598 andi t9,a0,3
604 PTR_ADDU a3,a0,a3
608 PTR_ADDIU a0,a0,4
610 bne a0,a3,L(wcopy_loop)
611 sw REG3,-4(a0)
634 C_STHI v1,UNIT(0)(a0)
635 PTR_ADDU a0,a0,a3
649 PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */
652 PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */
659 PREFETCH_FOR_STORE (1, a0)
660 PREFETCH_FOR_STORE (2, a0)
661 PREFETCH_FOR_STORE (3, a0)
665 sltu v1,t9,a0
668 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4)
671 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1)
680 sltu v1,t9,a0
684 PREFETCH_FOR_STORE (4, a0)
685 PREFETCH_FOR_STORE (5, a0)
700 C_ST t0,UNIT(0)(a0)
701 C_ST t1,UNIT(1)(a0)
702 C_ST REG2,UNIT(2)(a0)
703 C_ST REG3,UNIT(3)(a0)
704 C_ST REG4,UNIT(4)(a0)
705 C_ST REG5,UNIT(5)(a0)
706 C_ST REG6,UNIT(6)(a0)
707 C_ST REG7,UNIT(7)(a0)
725 C_ST t0,UNIT(8)(a0)
726 C_ST t1,UNIT(9)(a0)
727 C_ST REG2,UNIT(10)(a0)
728 C_ST REG3,UNIT(11)(a0)
729 C_ST REG4,UNIT(12)(a0)
730 C_ST REG5,UNIT(13)(a0)
731 C_ST REG6,UNIT(14)(a0)
732 C_ST REG7,UNIT(15)(a0)
733 PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */
734 bne a0,a3,L(ua_loop16w)
766 C_ST t0,UNIT(0)(a0)
767 C_ST t1,UNIT(1)(a0)
768 C_ST REG2,UNIT(2)(a0)
769 C_ST REG3,UNIT(3)(a0)
770 C_ST REG4,UNIT(4)(a0)
771 C_ST REG5,UNIT(5)(a0)
772 C_ST REG6,UNIT(6)(a0)
773 C_ST REG7,UNIT(7)(a0)
774 PTR_ADDIU a0,a0,UNIT(8)
783 PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */
789 PTR_ADDIU a0,a0,UNIT(1)
791 bne a0,a3,L(ua_wordCopy_loop)
792 C_ST v1,UNIT(-1)(a0)
797 PTR_ADDU a3,a0,a2 /* a3 is the last dst address */
800 PTR_ADDIU a0,a0,1
802 bne a0,a3,L(ua_smallCopy_loop)
803 sb v1,-1(a0)
824 PTR_ADDU REG6, a0, a3; /* REG6 is the dst address after loop. */ \
831 PTR_ADDIU a0, a0, UNIT(1); /* Increment destination pointer. */ \
834 bne a0, REG6,L(r6_ua_wordcopy##BYTEOFFSET); \
835 C_ST REG3, UNIT(-1)(a0); \