Lines Matching refs:r5
34 SETUP_GOT_ACCESS(r5,got_label)
35 addis r5,r5,_GLOBAL_OFFSET_TABLE_-got_label@ha
36 addi r5,r5,_GLOBAL_OFFSET_TABLE_-got_label@l
41 lwz r5,_rtld_local_ro@got(r5)
43 lwz r5,_rtld_global_ro@got(r5)
47 lwz r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+LOWORD(r5)
49 lwz r5,_dl_hwcap@got(r5)
52 lwz r5,LOWORD(r5)
55 lis r5,(_dl_hwcap+LOWORD)@ha
56 lwz r5,(_dl_hwcap+LOWORD)@l(r5)
58 andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
60 la r5,((JB_VRS)*4)(3)
61 andi. r6,r5,0xf
65 addi r6,r5,16
66 lvsl v0,0,r5
67 lvx v1,0,r5
68 addi r5,r5,32
75 load_misaligned_vmx_lo_loaded(v21,v22,v0,r5,r6)
76 load_misaligned_vmx_lo_loaded(v22,v23,v0,r6,r5)
77 load_misaligned_vmx_lo_loaded(v23,v24,v0,r5,r6)
78 load_misaligned_vmx_lo_loaded(v24,v25,v0,r6,r5)
79 load_misaligned_vmx_lo_loaded(v25,v26,v0,r5,r6)
80 load_misaligned_vmx_lo_loaded(v26,v27,v0,r6,r5)
81 load_misaligned_vmx_lo_loaded(v27,v28,v0,r5,r6)
82 load_misaligned_vmx_lo_loaded(v28,v29,v0,r6,r5)
83 load_misaligned_vmx_lo_loaded(v29,v30,v0,r5,r6)
84 load_misaligned_vmx_lo_loaded(v30,v31,v0,r6,r5)
85 lvx v1,0,r5
89 addi r6,r5,16
90 lvx v20,0,r5
91 addi r5,r5,32
94 lvx v22,0,r5
95 addi r5,r5,32
98 lvx v24,0,r5
99 addi r5,r5,32
102 lvx v26,0,r5
103 addi r5,r5,32
106 lvx v28,0,r5
107 addi r5,r5,32
110 lvx v30,0,r5
155 lwz r5,(JB_CR*4)(r3)
162 mtcrf 0xFF,r5