Lines Matching refs:r6
77 PTR_MANGLE (r5, r6)
95 PTR_MANGLE2 (r0, r6)
135 ld r6,.LC__dl_hwcap@toc(r2)
138 ld r6,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r6)
140 ld r6,0(r6) /* Load extern _dl_hwcap. */
142 andis. r6,r6,(PPC_FEATURE_HAS_ALTIVEC >> 16)
145 andi. r6,r5,0xf
148 addi r6,r5,16
153 addi r6,r5,-16
170 save_misaligned_vmx(v20,v2,v0,v3,r5,r6)
171 save_misaligned_vmx(v21,v20,v0,v3,r6,r5)
172 save_misaligned_vmx(v22,v21,v0,v3,r5,r6)
173 save_misaligned_vmx(v23,v22,v0,v3,r6,r5)
174 save_misaligned_vmx(v24,v23,v0,v3,r5,r6)
175 save_misaligned_vmx(v25,v24,v0,v3,r6,r5)
176 save_misaligned_vmx(v26,v25,v0,v3,r5,r6)
177 save_misaligned_vmx(v27,v26,v0,v3,r6,r5)
178 save_misaligned_vmx(v28,v27,v0,v3,r5,r6)
179 save_misaligned_vmx(v29,v28,v0,v3,r6,r5)
180 save_misaligned_vmx(v30,v29,v0,v3,r5,r6)
181 save_misaligned_vmx(v31,v30,v0,v3,r6,r5)
183 lvx v2,0,r6
185 save_misaligned_vmx(v2,v31,v0,v3,r5,r6)
192 stvx 21,0,r6
193 addi r6,r6,32
196 stvx 23,0,r6
197 addi r6,r6,32
200 stvx 25,0,r6
201 addi r6,r6,32
204 stvx 27,0,r6
205 addi r6,r6,32
208 stvx 29,0,r6
209 addi r6,r6,32
211 stvx 31,0,r6
214 li r6,0