Searched refs:midr (Results 1 – 7 of 7) sorted by relevance
42 #define IS_THUNDERX(midr) (MIDR_IMPLEMENTOR(midr) == 'C' \ argument45 #define IS_THUNDERX2PA(midr) (MIDR_IMPLEMENTOR(midr) == 'B' \ argument47 #define IS_THUNDERX2(midr) (MIDR_IMPLEMENTOR(midr) == 'C' \ argument50 #define IS_FALKOR(midr) (MIDR_IMPLEMENTOR(midr) == 'Q' \ argument53 #define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \ argument55 #define IS_NEOVERSE_N1(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \ argument57 #define IS_NEOVERSE_N2(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \ argument59 #define IS_NEOVERSE_V1(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \ argument62 #define IS_EMAG(midr) (MIDR_IMPLEMENTOR(midr) == 'P' \ argument65 #define IS_KUNPENG920(midr) (MIDR_IMPLEMENTOR(midr) == 'H' \ argument[all …]
37 uint64_t midr; member58 return cpu_list[i].midr; in get_midr_from_mcpu()67 register uint64_t midr = UINT64_MAX; in init_cpu_features() local73 midr = get_midr_from_mcpu (mcpu); in init_cpu_features()78 if (midr == UINT64_MAX) in init_cpu_features()81 asm volatile ("mrs %0, midr_el1" : "=r"(midr)); in init_cpu_features()83 midr = 0; in init_cpu_features()86 cpu_features->midr_el1 = midr; in init_cpu_features()
41 (IS_THUNDERX (midr)43 : (IS_FALKOR (midr) || IS_PHECDA (midr)45 : (IS_THUNDERX2 (midr) || IS_THUNDERX2PA (midr)47 : (IS_NEOVERSE_N1 (midr) || IS_NEOVERSE_N2 (midr)48 || IS_NEOVERSE_V1 (midr)51 : (IS_A64FX (midr)
40 IS_KUNPENG920 (midr)42 : ((IS_FALKOR (midr) || IS_PHECDA (midr)) && zva_size == 6444 : (IS_EMAG (midr) && zva_size == 6447 : (IS_A64FX (midr)
35 ((IS_EMAG (midr)
29 uint64_t __attribute__((unused)) midr = \
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