Lines Matching refs:MFP
2 MFP Configuration for PXA2xx/PXA3xx Processors
7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
8 later PXA series processors. This document describes the existing MFP API,
14 Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
19 the MFP logic and the remaining SoC peripherals::
28 | PWM2 |--(PWM_OUT)-------->| MFP |
48 to this new MFP mechanism, here are several key points:
63 3. Low power state for each pin is now controlled by MFP, this means the
66 4. Wakeup detection is now controlled by MFP, PWER does not control the
68 (as defined in pxa3xx-regs.h) controls the wakeup from MFP
70 NOTE: with such a clear separation of MFP and GPIO, by GPIO<xx> we normally
71 mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical
74 MFP API Usage
92 (in addition to handle MFP configuration differences, they also handle
145 d) although PXA3xx MFP supports edge detection on each pin, the
152 MFP on PXA3xx
156 one MFP logic associated, and is controlled by one MFP register (MFPR).
188 MFP Design for PXA2xx/PXA3xx
192 MFP API is introduced to cover both series of processors.
206 2. processor-neutral bit definitions for a possible MFP configuration
238 * a possible MFP configuration is represented by a 32-bit integer
240 * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
249 * MFP_CFG_DEFAULT - default MFP configuration value, with