Lines Matching refs:side
77 the ODT on the DRAM side and controller side are
81 the DRAM side driver strength in ohms. Default
85 the DRAM side ODT strength in ohms. Default value
89 the phy side CA line (incluing command line,
94 the PHY side DQ line (including DQS/DQ/DM line)
98 the PHY side ODT strength. Default value is 240.
103 the ODT on the DRAM side and controller side are
107 the DRAM side driver strength in ohms. Default
111 the DRAM side ODT strength in ohms. Default value
115 the PHY side CA line (including command line,
120 the PHY side DQ line (including DQS/DQ/DM line)
124 the phy side odt strength, default value is 240.
129 ddr3_odt_dis_freq, the ODT on the DRAM side and
130 controller side are both disabled.
133 the DRAM side driver strength in ohms. Default
137 the DRAM side ODT on DQS/DQ line strength in ohms.
141 the DRAM side ODT on CA line strength in ohms.
145 the PHY side CA line (including command address
149 the PHY side clock line and CS line driver
153 the PHY side DQ line (including DQS/DQ/DM line)
157 the PHY side ODT strength. Default value is 60.