Lines Matching refs:topckgen
63 <&topckgen CLK_TOP_UNIVPLL_D2>,
64 <&topckgen CLK_TOP_CCI400_SEL>,
65 <&topckgen CLK_TOP_VDEC_SEL>,
66 <&topckgen CLK_TOP_VCODECPLL>,
68 <&topckgen CLK_TOP_VENC_LT_SEL>,
69 <&topckgen CLK_TOP_VCODECPLL_370P5>;
78 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
79 <&topckgen CLK_TOP_CCI400_SEL>,
80 <&topckgen CLK_TOP_VDEC_SEL>,
83 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
84 <&topckgen CLK_TOP_UNIVPLL_D2>,
85 <&topckgen CLK_TOP_VCODECPLL>;
106 clocks = <&topckgen CLK_TOP_VENC_SEL>;
108 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
109 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
127 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
129 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
130 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;