Lines Matching refs:terms
69 Active bank a to active bank b in terms of number of clock cycles.
76 Internal WRITE-to-READ command delay in terms of number of clock cycles.
83 Exit power-down to next valid command delay in terms of number of clock
90 Internal READ to PRECHARGE command delay in terms of number of clock
97 CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
104 Row precharge time (all banks) in terms of number of clock cycles.
111 RAS-to-CAS delay in terms of number of clock cycles. Obtained from
118 WRITE recovery time in terms of number of clock cycles. Obtained from
125 Row active time in terms of number of clock cycles. Obtained from device
133 SELF REFRESH) in terms of number of clock cycles. Obtained from device
140 Four-bank activate window in terms of number of clock cycles. Obtained