Lines Matching refs:reset
4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
22 intel,global-reset:
23 description: Global reset register offset and bit offset.
31 "#reset-cells":
35 First cell is reset request register offset.
36 Second cell is bit offset in reset request register.
37 Third cell is bit offset in reset status register.
38 For LGM SoC, reset cell count is 2 as bit offset in
39 reset request and reset status registers is same. Whereas
45 - intel,global-reset
46 - "#reset-cells"
52 rcu0: reset-controller@e0000000 {
55 intel,global-reset = <0x10 30>;
56 #reset-cells = <2>;