Lines Matching refs:assigned
35 assigned-clocks:
39 assigned-clock-parents:
43 assigned-clock-rates:
53 - assigned-clocks
54 - assigned-clock-parents
69 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
72 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
73 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
91 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
92 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
161 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
162 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
163 assigned-clock-rates = <1536000>;