Lines Matching refs:writes
76 are burned by the fact that PCI bus writes are posted asynchronously. A
78 writes have occurred in the specific cases the author cares. This kind
107 outstanding DMA writes from that bus, since for some devices the result of
110 next readb() call has no relation to any previous DMA writes
176 Note that posted writes are not strictly ordered against a spinlock, see
305 * Uncached - CPU-side caches are bypassed, and all reads and writes are handled
313 * No repetition - The CPU may not issue multiple reads or writes for a single
316 being issued to the device, and multiple writes are not combined into larger
317 writes. This may or may not be enforced when using __raw I/O accessors or
323 On many platforms and buses (e.g. PCI), writes issued through ioremap()
341 * The CPU may combine several writes into a single larger write.
344 performance of writes. It can also be used for other blocks of memory in
360 * The CPU may cache writes issued to and reads from the device, and serve reads
364 writes to reach the device in a timely manner (and not be stuck in the CPU
366 rarely useful these days, as framebuffer drivers usually perform writes only,
375 means that writes can appear to "complete" from the point of view of the
377 still ordered with respect to other writes and reads from the same device, but
392 platform-specific or they derive benefit from non-posted writes where
398 ioremap_np() should never be used for PCI drivers. PCI memory space writes are
404 guarantees. A CPU may still choose to issue other reads or writes before a
476 require non-posted writes for certain buses (see the nonposted-mmio and