Lines Matching refs:loads
178 perceived by the loads made by another CPU in the same order as the stores were
247 (*) Overlapping loads and stores within a particular CPU will appear to be
275 (*) It _must_not_ be assumed that independent loads and stores will be issued
369 deferral and combination of memory operations; speculative loads; speculative
388 to have any effect on loads.
401 where two loads are performed such that the second depends on the result
407 A data dependency barrier is a partial ordering on interdependent loads
408 only; it is not required to have any effect on stores, independent loads
409 or overlapping loads.
417 touched by the load will be perceptible to any loads issued after the data
441 A read barrier is a partial ordering on loads only; it is not required to
458 A general memory barrier is a partial ordering over both loads and stores.
702 load from 'a' with other loads from 'a'. Without the WRITE_ONCE(),
877 (*) Control dependencies can order prior loads against later stores.
879 Not prior loads against later loads, nor prior stores against
882 later loads, smp_mb().
971 match the loads after the read barrier or the data dependency barrier, and vice
1025 loads. Consider the following sequence of events:
1107 subsequent loads +-------+ | |
1111 And thirdly, a read barrier acts as a partial order on loads. Consider the
1197 Even though the two loads of A both occur after the load of B, they may both
1257 Many CPUs speculate with loads: that is they see that they will need to load an
1259 other loads, and so do the load in advance - even though they haven't actually
1377 CPU 2 executes its load before its store, and CPU 3 loads from Y before
1378 it loads from X. The question is then "Can CPU 3's load from X return 0?"
1482 subsequent loads in all cases. This means that cpu3() can see cpu0()'s
1541 (*) The compiler is within its rights to reorder loads and stores
1543 rights to reorder loads to the same variable. This means that
1558 (*) The compiler is within its rights to merge successive loads from
1754 The compiler can also invent loads. These are usually less
1757 invented loads.
1797 loads followed by a pair of 32-bit stores. This would result in
1833 to issue the loads in the correct order (eg. `a[b]` would have to load
2207 If a wakeup does occur, one (at least) of the two loads must see 1. If, on
2208 the other hand, a wakeup does not occur, both loads might see 0.
2213 the two loads would be guaranteed to see 1.
2237 order multiple stores before the wake-up with respect to loads of those stored
2718 their own loads and stores as if they had happened in program order.
2785 (*) loads are more likely to need to be completed immediately to permit
2789 (*) loads may be done speculatively, and the result discarded should it prove
2792 (*) loads may be done speculatively, leading to the result having been fetched
2798 (*) loads and stores may be combined to improve performance when talking to
2844 where a given CPU might reorder successive loads to the same location.