Lines Matching refs:C
123 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
126 static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
127 [C(L1D)] = {
128 [C(OP_READ)] = {
129 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
130 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
132 [C(OP_WRITE)] = {
133 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
134 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
136 [C(OP_PREFETCH)] = {
137 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
138 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
141 [C(L1I)] = {
142 [C(OP_READ)] = {
143 [C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS,
144 [C(RESULT_MISS)] = PERF_COUNT_ARC_ICM,
146 [C(OP_WRITE)] = {
147 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
148 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
150 [C(OP_PREFETCH)] = {
151 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
152 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
155 [C(LL)] = {
156 [C(OP_READ)] = {
157 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
158 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
160 [C(OP_WRITE)] = {
161 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
162 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
164 [C(OP_PREFETCH)] = {
165 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
166 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
169 [C(DTLB)] = {
170 [C(OP_READ)] = {
171 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
172 [C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB,
175 [C(OP_WRITE)] = {
176 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
177 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
179 [C(OP_PREFETCH)] = {
180 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
181 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
184 [C(ITLB)] = {
185 [C(OP_READ)] = {
186 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
187 [C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB,
189 [C(OP_WRITE)] = {
190 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
191 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
193 [C(OP_PREFETCH)] = {
194 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
195 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
198 [C(BPU)] = {
199 [C(OP_READ)] = {
200 [C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
201 [C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES,
203 [C(OP_WRITE)] = {
204 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
205 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
207 [C(OP_PREFETCH)] = {
208 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
209 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
212 [C(NODE)] = {
213 [C(OP_READ)] = {
214 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
215 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
217 [C(OP_WRITE)] = {
218 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
219 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
221 [C(OP_PREFETCH)] = {
222 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
223 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,