Lines Matching refs:UPDATE_VAL
139 #define UPDATE_VAL 1 macro
213 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
219 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
237 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE)); in hsdk_init_memory_bridge()
243 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in hsdk_init_memory_bridge()
249 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN)); in hsdk_init_memory_bridge()
255 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO)); in hsdk_init_memory_bridge()
261 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO)); in hsdk_init_memory_bridge()
267 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST)); in hsdk_init_memory_bridge()
273 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET)); in hsdk_init_memory_bridge()
279 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO)); in hsdk_init_memory_bridge()
285 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU)); in hsdk_init_memory_bridge()
291 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS)); in hsdk_init_memory_bridge()
302 writel(UPDATE_VAL, CREG_PAE_UPDT); in hsdk_init_memory_bridge()