Lines Matching refs:writel
209 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
210 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
211 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
212 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
213 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
215 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
216 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
217 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
218 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
219 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
232 writel(reg, CREG_AXI_M_HS_CORE_BOOT); in hsdk_init_memory_bridge()
233 writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE)); in hsdk_init_memory_bridge()
234 writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE)); in hsdk_init_memory_bridge()
235 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE)); in hsdk_init_memory_bridge()
236 writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE)); in hsdk_init_memory_bridge()
237 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE)); in hsdk_init_memory_bridge()
239 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in hsdk_init_memory_bridge()
240 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in hsdk_init_memory_bridge()
241 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in hsdk_init_memory_bridge()
242 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in hsdk_init_memory_bridge()
243 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in hsdk_init_memory_bridge()
245 writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN)); in hsdk_init_memory_bridge()
246 writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN)); in hsdk_init_memory_bridge()
247 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN)); in hsdk_init_memory_bridge()
248 writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN)); in hsdk_init_memory_bridge()
249 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN)); in hsdk_init_memory_bridge()
251 writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO)); in hsdk_init_memory_bridge()
252 writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO)); in hsdk_init_memory_bridge()
253 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO)); in hsdk_init_memory_bridge()
254 writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO)); in hsdk_init_memory_bridge()
255 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO)); in hsdk_init_memory_bridge()
257 writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO)); in hsdk_init_memory_bridge()
258 writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO)); in hsdk_init_memory_bridge()
259 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO)); in hsdk_init_memory_bridge()
260 writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO)); in hsdk_init_memory_bridge()
261 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO)); in hsdk_init_memory_bridge()
263 writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST)); in hsdk_init_memory_bridge()
264 writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST)); in hsdk_init_memory_bridge()
265 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST)); in hsdk_init_memory_bridge()
266 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST)); in hsdk_init_memory_bridge()
267 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST)); in hsdk_init_memory_bridge()
269 writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET)); in hsdk_init_memory_bridge()
270 writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET)); in hsdk_init_memory_bridge()
271 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET)); in hsdk_init_memory_bridge()
272 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET)); in hsdk_init_memory_bridge()
273 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET)); in hsdk_init_memory_bridge()
275 writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO)); in hsdk_init_memory_bridge()
276 writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO)); in hsdk_init_memory_bridge()
277 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO)); in hsdk_init_memory_bridge()
278 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO)); in hsdk_init_memory_bridge()
279 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO)); in hsdk_init_memory_bridge()
281 writel(0x77777777, CREG_AXI_M_SLV0(M_GPU)); in hsdk_init_memory_bridge()
282 writel(0x77777777, CREG_AXI_M_SLV1(M_GPU)); in hsdk_init_memory_bridge()
283 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU)); in hsdk_init_memory_bridge()
284 writel(0x76543210, CREG_AXI_M_OFT1(M_GPU)); in hsdk_init_memory_bridge()
285 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU)); in hsdk_init_memory_bridge()
287 writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS)); in hsdk_init_memory_bridge()
288 writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS)); in hsdk_init_memory_bridge()
289 writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS)); in hsdk_init_memory_bridge()
290 writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS)); in hsdk_init_memory_bridge()
291 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS)); in hsdk_init_memory_bridge()
301 writel(0x00000000, CREG_PAE); in hsdk_init_memory_bridge()
302 writel(UPDATE_VAL, CREG_PAE_UPDT); in hsdk_init_memory_bridge()