Lines Matching refs:assigned
222 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
224 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
225 assigned-clock-rates = <0>, <100000000>;
249 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
251 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
252 assigned-clock-rates = <0>, <100000000>;
393 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
396 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
397 assigned-clock-rates = <0>, <884736000>, <12288000>;
429 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
432 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
433 assigned-clock-rates = <0>, <884736000>, <36864000>;
440 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
443 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
444 assigned-clock-rates = <0>, <884736000>, <36864000>;
455 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
456 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
463 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
464 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
508 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
509 assigned-clock-rates = <400000000>;