Lines Matching refs:topckgen
226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
553 <&topckgen CLK_TOP_FLASH_SEL>;
567 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
568 <&topckgen CLK_TOP_SPI1_SEL>,
581 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
582 <&topckgen CLK_TOP_SPI2_SEL>,
615 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
637 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
638 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
639 <&topckgen CLK_TOP_AUD_48K_TIMING>,
640 <&topckgen CLK_TOP_AUD_44K_TIMING>,
641 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
642 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
643 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
644 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
645 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
646 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
647 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
648 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
649 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
650 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
651 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
652 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
706 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
707 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
708 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
709 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
710 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
711 <&topckgen CLK_TOP_AUD2PLL_90M>;
722 <&topckgen CLK_TOP_MSDC30_0_SEL>;
733 <&topckgen CLK_TOP_MSDC30_1_SEL>;
770 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
867 <&topckgen CLK_TOP_ETHIF_SEL>;
885 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
908 <&topckgen CLK_TOP_ETHIF_SEL>;
926 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
968 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,