Lines Matching refs:rp
46 #define checkuart(rp, rv, family_id, family) \ argument
48 ldr rp, =family_id ; \
50 cmp rp, rv ; \
52 ldreq rp, =UARTA_##family ; \
56 .macro addruart, rp, rv, tmp
57 adr \rp, 99f @ actual addr of 99f
58 ldr \rv, [\rp] @ linked addr is stored there
59 sub \rv, \rv, \rp @ offset between the two
60 ldr \rp, [\rp, #4] @ linked brcmstb_uart_config
61 sub \tmp, \rp, \rv @ actual brcmstb_uart_config
62 ldr \rp, [\tmp] @ Load brcmstb_uart_config
63 cmp \rp, #1 @ needs initialization?
70 ldr \rp, =ARM_CPU_PART_MASK
71 and \rv, \rv, \rp
72 ldr \rp, =ARM_CPU_PART_BRAHMA_B53 @ check for B53 CPU
73 cmp \rv, \rp
79 ldreq \rp, =SUN_TOP_CTRL_BASE_V7
82 10: ldrne \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA
83 ldr \rv, [\rp, #0] @ get register contents
88 20: checkuart(\rp, \rv, 0x33900000, 3390)
89 21: checkuart(\rp, \rv, 0x07211600, 72116)
90 22: checkuart(\rp, \rv, 0x72160000, 7216)
91 23: checkuart(\rp, \rv, 0x07216400, 72164)
92 24: checkuart(\rp, \rv, 0x07216500, 72165)
93 25: checkuart(\rp, \rv, 0x72500000, 7250)
94 26: checkuart(\rp, \rv, 0x72550000, 7255)
95 27: checkuart(\rp, \rv, 0x72600000, 7260)
96 28: checkuart(\rp, \rv, 0x72680000, 7268)
97 29: checkuart(\rp, \rv, 0x72710000, 7271)
98 30: checkuart(\rp, \rv, 0x72780000, 7278)
99 31: checkuart(\rp, \rv, 0x73640000, 7364)
100 32: checkuart(\rp, \rv, 0x73660000, 7366)
101 33: checkuart(\rp, \rv, 0x07437100, 74371)
102 34: checkuart(\rp, \rv, 0x74390000, 7439)
103 35: checkuart(\rp, \rv, 0x74450000, 7445)
106 90: mov \rp, #0
110 91: str \rp, [\tmp, #4] @ Store in brcmstb_uart_phys
111 cmp \rp, #0 @ Valid UART address?
113 str \rp, [\tmp, #8] @ Store 0 in brcmstb_uart_virt
115 92: and \rv, \rp, #0xffffff @ offset within 16MB section
126 100: ldr \rp, [\tmp, #4] @ Load brcmstb_uart_phys