Lines Matching refs:r5
66 bl __lookup_processor_type @ r5=procinfo r9=cpuid
67 movs r10, r5 @ invalid processor (r5=0)?
102 bl __lookup_processor_type @ r5=procinfo r9=cpuid
103 movs r10, r5 @ invalid processor?
273 ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET
275 sub r6, r6, r5 @ Minimum size of region to map
285 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
294 ldr r5,=(PMSAv7_AP_PL1RW_PL0RW | PMSAv7_RGN_NORMAL)
296 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ PHYS_OFFSET, shared, enabled
298 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ PHYS_OFFSET, shared, enabled
306 ldr r5,=(PMSAv7_ACR_XN | PMSAv7_RGN_STRONGLY_ORDERED | PMSAv7_AP_PL1RW_PL0NA)
309 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ 0x0, BG region, enabled
311 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE r12 @ 0x0, BG region, enabled
318 ldr r5,=(PMSAv7_AP_PL1RO_PL0NA | PMSAv7_RGN_NORMAL)
328 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
330 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
343 ldr r5, =CONFIG_XIP_PHYS_ADDR @ ROM start
348 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED)
351 AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0
353 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(0)])
357 ldr r5, =KERNEL_START
362 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED)
365 AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1
367 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(1)])
373 ldr r5, =CONFIG_XIP_PHYS_ADDR
374 cmp r6, r5
375 movcs r6, r5
382 mov r5, #0
386 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
389 AR_CLASS(mcr p15, 0, r5, c6, c9, 0) @ PRBAR2
391 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(2)])
397 ldr r5, =KERNEL_END
399 cmp r5, r6
400 movcc r5, r6
402 ldr r5, =KERNEL_END
407 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
410 AR_CLASS(mcr p15, 0, r5, c6, c9, 4) @ PRBAR3
412 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(3)])
417 ldr r5, =(_exiprom)
419 cmp r5, r6
420 movcs r5, r6
430 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
439 str r5, [r12, #PMSAv8_RBAR_A(0)]
442 mcr p15, 0, r5, c6, c10, 0 @ PRBAR4
476 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
480 mov r5, #MPU_RNG_SIZE
482 mla r3, r4, r5, r3
494 ldr r5, [r3, #MPU_RGN_DRACR]
496 setup_region r0, r5, r6, PMSAv7_DATA_SIDE
498 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE
513 mov r5, #MPU_RNG_SIZE
515 mla r3, r4, r5, r3
524 ldr r5, [r3, #MPU_RGN_PRBAR]
527 mcr p15, 0, r5, c6, c3, 0 @ PRBAR