Lines Matching refs:clkdm_offs
317 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
327 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
339 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
348 .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
360 .clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
369 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
381 .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
393 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
405 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
417 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
427 .clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
439 .clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
450 .clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
459 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
469 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
478 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
490 .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
500 .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
511 .clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
520 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
532 .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
542 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
550 .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
562 .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
572 .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
581 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
593 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
605 .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
617 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
627 .clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
639 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
651 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
663 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
675 .clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
685 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,