Lines Matching refs:rt
22 .macro v7m_cache_read, rt, reg
23 movw \rt, #:lower16:BASEADDR_V7M_SCB + \reg
24 movt \rt, #:upper16:BASEADDR_V7M_SCB + \reg
25 ldr \rt, [\rt]
28 .macro v7m_cacheop, rt, tmp, op, c = al
31 str\c \rt, [\tmp]
35 .macro read_ccsidr, rt
36 v7m_cache_read \rt, V7M_SCB_CCSIDR
39 .macro read_clidr, rt
40 v7m_cache_read \rt, V7M_SCB_CLIDR
43 .macro write_csselr, rt, tmp
44 v7m_cacheop \rt, \tmp, V7M_SCB_CSSELR
50 .macro dcisw, rt, tmp
51 v7m_cacheop \rt, \tmp, V7M_SCB_DCISW
57 .macro dccisw, rt, tmp
58 v7m_cacheop \rt, \tmp, V7M_SCB_DCCISW
65 .macro dccimvac\c, rt, tmp
66 v7m_cacheop \rt, \tmp, V7M_SCB_DCCIMVAC, \c
74 .macro dcimvac\c, rt, tmp
75 v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC, \c
82 .macro dccmvau, rt, tmp
83 v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAU
89 .macro dccmvac, rt, tmp
90 v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAC
96 .macro icimvau, rt, tmp
97 v7m_cacheop \rt, \tmp, V7M_SCB_ICIMVAU
104 .macro invalidate_icache, rt
105 v7m_cacheop \rt, \rt, V7M_SCB_ICIALLU
106 mov \rt, #0
113 .macro invalidate_bp, rt
114 v7m_cacheop \rt, \rt, V7M_SCB_BPIALL
115 mov \rt, #0