Lines Matching refs:topckgen
90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
290 <&topckgen CLK_TOP_VDEC_SEL>;
321 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
480 clocks = <&topckgen CLK_TOP_PWM_SEL>,
554 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
555 <&topckgen CLK_TOP_SPI_SEL>,
565 clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>;
577 clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>;
633 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
634 <&topckgen CLK_TOP_SPI_SEL>,
646 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
647 <&topckgen CLK_TOP_SPI_SEL>,
659 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
660 <&topckgen CLK_TOP_SPI_SEL>,
672 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
673 <&topckgen CLK_TOP_SPI_SEL>,
740 <&topckgen CLK_TOP_ETHER_125M_SEL>,
741 <&topckgen CLK_TOP_ETHER_50M_SEL>;
742 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
743 <&topckgen CLK_TOP_ETHER_50M_SEL>;
744 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
745 <&topckgen CLK_TOP_APLL1_D3>;
774 <&topckgen CLK_TOP_AXI_SEL>,
785 <&topckgen CLK_TOP_AXI_SEL>,
800 clocks = <&topckgen CLK_TOP_USB30_SEL>;
815 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
864 clocks = <&topckgen CLK_TOP_USB30_SEL>;
879 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
928 clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
960 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,