Lines Matching refs:topckgen
243 clocks = <&topckgen CLK_TOP_HIF_SEL>;
252 <&topckgen CLK_TOP_AXI_SEL>;
285 topckgen: topckgen@10210000 { label
286 compatible = "mediatek,mt7622-topckgen",
325 clocks = <&topckgen CLK_TOP_RTC>;
389 clocks = <&topckgen CLK_TOP_UART_SEL>,
400 clocks = <&topckgen CLK_TOP_UART_SEL>,
411 clocks = <&topckgen CLK_TOP_UART_SEL>,
422 clocks = <&topckgen CLK_TOP_UART_SEL>,
432 clocks = <&topckgen CLK_TOP_PWM_SEL>,
491 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
492 <&topckgen CLK_TOP_SPI0_SEL>,
562 <&topckgen CLK_TOP_FLASH_SEL>;
573 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
574 <&topckgen CLK_TOP_SPI1_SEL>,
587 clocks = <&topckgen CLK_TOP_UART_SEL>,
605 <&topckgen CLK_TOP_AUD1_SEL>,
606 <&topckgen CLK_TOP_AUD2_SEL>,
607 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
608 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
609 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
610 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
611 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
612 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
613 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
614 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
615 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
616 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
617 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
618 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
619 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
620 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
672 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
673 <&topckgen CLK_TOP_A2SYS_HP_SEL>,
674 <&topckgen CLK_TOP_A1SYS_HP_DIV>,
675 <&topckgen CLK_TOP_A2SYS_HP_DIV>;
676 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
677 <&topckgen CLK_TOP_AUD2PLL>;
687 <&topckgen CLK_TOP_MSDC50_0_SEL>;
699 <&topckgen CLK_TOP_AXI_SEL>;
898 clocks = <&topckgen CLK_TOP_ETH_500M>;
930 clocks = <&topckgen CLK_TOP_ETH_SEL>,
939 <&topckgen CLK_TOP_SGMIIPLL>,