Lines Matching refs:topckgen
356 topckgen: clock-controller@10000000 { label
357 compatible = "mediatek,mt8173-topckgen";
468 clocks = <&topckgen CLK_TOP_MM_SEL>;
474 clocks = <&topckgen CLK_TOP_MM_SEL>,
475 <&topckgen CLK_TOP_VENC_SEL>;
481 clocks = <&topckgen CLK_TOP_MM_SEL>;
487 clocks = <&topckgen CLK_TOP_MM_SEL>;
494 clocks = <&topckgen CLK_TOP_MM_SEL>,
495 <&topckgen CLK_TOP_VENC_LT_SEL>;
562 clocks = <&topckgen CLK_TOP_SCP_SEL>;
760 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
761 <&topckgen CLK_TOP_SPI_SEL>,
785 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
854 <&topckgen CLK_TOP_AUDIO_SEL>,
855 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
856 <&topckgen CLK_TOP_APLL1_DIV0>,
857 <&topckgen CLK_TOP_APLL2_DIV0>,
858 <&topckgen CLK_TOP_I2S0_M_SEL>,
859 <&topckgen CLK_TOP_I2S1_M_SEL>,
860 <&topckgen CLK_TOP_I2S2_M_SEL>,
861 <&topckgen CLK_TOP_I2S3_M_SEL>,
862 <&topckgen CLK_TOP_I2S3_B_SEL>;
873 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
874 <&topckgen CLK_TOP_AUD_2_SEL>;
875 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
876 <&topckgen CLK_TOP_APLL2>;
884 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
894 <&topckgen CLK_TOP_AXI_SEL>;
904 <&topckgen CLK_TOP_AXI_SEL>;
914 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
929 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
944 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
987 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
1326 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1403 <&topckgen CLK_TOP_UNIVPLL_D2>,
1404 <&topckgen CLK_TOP_CCI400_SEL>,
1405 <&topckgen CLK_TOP_VDEC_SEL>,
1406 <&topckgen CLK_TOP_VCODECPLL>,
1408 <&topckgen CLK_TOP_VENC_LT_SEL>,
1409 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1418 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1419 <&topckgen CLK_TOP_CCI400_SEL>,
1420 <&topckgen CLK_TOP_VDEC_SEL>,
1423 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1424 <&topckgen CLK_TOP_UNIVPLL_D2>,
1425 <&topckgen CLK_TOP_VCODECPLL>;
1472 clocks = <&topckgen CLK_TOP_VENC_SEL>;
1474 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1475 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1523 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1525 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1527 <&topckgen CLK_TOP_VCODECPLL_370P5>;