Lines Matching refs:topckgen
370 topckgen: syscon@10000000 { label
371 compatible = "mediatek,mt8183-topckgen", "syscon";
428 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
443 clocks = <&topckgen CLK_TOP_MUX_MFG>;
475 clocks = <&topckgen CLK_TOP_MUX_MM>,
497 clocks = <&topckgen CLK_TOP_MUX_CAM>,
515 clocks = <&topckgen CLK_TOP_MUX_IMG>,
538 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
539 <&topckgen CLK_TOP_MUX_DSP>,
556 clocks = <&topckgen CLK_TOP_MUX_DSP1>;
564 clocks = <&topckgen CLK_TOP_MUX_DSP2>;
591 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
613 clocks = <&topckgen CLK_TOP_CLK13M>;
739 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
740 <&topckgen CLK_TOP_MUX_SPI>,
888 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
927 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
928 <&topckgen CLK_TOP_MUX_SPI>,
954 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
955 <&topckgen CLK_TOP_MUX_SPI>,
967 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
968 <&topckgen CLK_TOP_MUX_SPI>,
1040 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1041 <&topckgen CLK_TOP_MUX_SPI>,
1053 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1054 <&topckgen CLK_TOP_MUX_SPI>,
1146 <&topckgen CLK_TOP_MUX_AUDIO>,
1147 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
1148 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
1149 <&topckgen CLK_TOP_MUX_AUD_1>,
1150 <&topckgen CLK_TOP_APLL1_CK>,
1151 <&topckgen CLK_TOP_MUX_AUD_2>,
1152 <&topckgen CLK_TOP_APLL2_CK>,
1153 <&topckgen CLK_TOP_MUX_AUD_ENG1>,
1154 <&topckgen CLK_TOP_APLL1_D8>,
1155 <&topckgen CLK_TOP_MUX_AUD_ENG2>,
1156 <&topckgen CLK_TOP_APLL2_D8>,
1157 <&topckgen CLK_TOP_MUX_APLL_I2S0>,
1158 <&topckgen CLK_TOP_MUX_APLL_I2S1>,
1159 <&topckgen CLK_TOP_MUX_APLL_I2S2>,
1160 <&topckgen CLK_TOP_MUX_APLL_I2S3>,
1161 <&topckgen CLK_TOP_MUX_APLL_I2S4>,
1162 <&topckgen CLK_TOP_MUX_APLL_I2S5>,
1163 <&topckgen CLK_TOP_APLL12_DIV0>,
1164 <&topckgen CLK_TOP_APLL12_DIV1>,
1165 <&topckgen CLK_TOP_APLL12_DIV2>,
1166 <&topckgen CLK_TOP_APLL12_DIV3>,
1167 <&topckgen CLK_TOP_APLL12_DIV4>,
1168 <&topckgen CLK_TOP_APLL12_DIVB>,
1169 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
1221 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
1233 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
1307 clocks = <&topckgen CLK_TOP_MFGPLL_CK>;