Lines Matching refs:assigned
516 assigned-clocks = <&k3_clks 157 371>;
517 assigned-clock-parents = <&k3_clks 157 400>;
518 assigned-clock-rates = <24576000>; /* for 48KHz */
570 assigned-clocks = <&k3_clks 152 1>,
574 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
647 assigned-clocks = <&wiz0_pll1_refclk>;
648 assigned-clock-parents = <&cmn_refclk1>;
652 assigned-clocks = <&wiz0_refclk_dig>;
653 assigned-clock-parents = <&cmn_refclk1>;
657 assigned-clocks = <&wiz1_pll1_refclk>;
658 assigned-clock-parents = <&cmn_refclk1>;
662 assigned-clocks = <&wiz1_refclk_dig>;
663 assigned-clock-parents = <&cmn_refclk1>;
667 assigned-clocks = <&wiz2_pll1_refclk>;
668 assigned-clock-parents = <&cmn_refclk1>;
672 assigned-clocks = <&wiz2_refclk_dig>;
673 assigned-clock-parents = <&cmn_refclk1>;
677 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
678 assigned-clock-parents = <&wiz0_pll1_refclk>;
690 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
691 assigned-clock-parents = <&wiz1_pll1_refclk>;
703 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
704 assigned-clock-parents = <&wiz2_pll1_refclk>;