Lines Matching refs:vmcr
267 struct vgic_vmcr vmcr; in vgic_mmio_read_vcpuif() local
270 vgic_get_vmcr(vcpu, &vmcr); in vgic_mmio_read_vcpuif()
274 val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT; in vgic_mmio_read_vcpuif()
275 val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT; in vgic_mmio_read_vcpuif()
276 val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT; in vgic_mmio_read_vcpuif()
277 val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT; in vgic_mmio_read_vcpuif()
278 val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT; in vgic_mmio_read_vcpuif()
279 val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT; in vgic_mmio_read_vcpuif()
290 val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >> in vgic_mmio_read_vcpuif()
294 val = vmcr.bpr; in vgic_mmio_read_vcpuif()
297 val = vmcr.abpr; in vgic_mmio_read_vcpuif()
315 struct vgic_vmcr vmcr; in vgic_mmio_write_vcpuif() local
317 vgic_get_vmcr(vcpu, &vmcr); in vgic_mmio_write_vcpuif()
321 vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0); in vgic_mmio_write_vcpuif()
322 vmcr.grpen1 = !!(val & GIC_CPU_CTRL_EnableGrp1); in vgic_mmio_write_vcpuif()
323 vmcr.ackctl = !!(val & GIC_CPU_CTRL_AckCtl); in vgic_mmio_write_vcpuif()
324 vmcr.fiqen = !!(val & GIC_CPU_CTRL_FIQEn); in vgic_mmio_write_vcpuif()
325 vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR); in vgic_mmio_write_vcpuif()
326 vmcr.eoim = !!(val & GIC_CPU_CTRL_EOImodeNS); in vgic_mmio_write_vcpuif()
337 vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) & in vgic_mmio_write_vcpuif()
341 vmcr.bpr = val; in vgic_mmio_write_vcpuif()
344 vmcr.abpr = val; in vgic_mmio_write_vcpuif()
348 vgic_set_vmcr(vcpu, &vmcr); in vgic_mmio_write_vcpuif()