Lines Matching refs:Rt
23 #define A64_COMP_BRANCH(sf, Rt, offset, type) \ argument
24 aarch64_insn_gen_comp_branch_imm(0, offset, Rt, A64_VARIANT(sf), \
26 #define A64_CBZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, ZERO) argument
27 #define A64_CBNZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, NONZERO) argument
56 #define A64_LS_REG(Rt, Rn, Rm, size, type) \ argument
57 aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \
70 #define A64_LS_PAIR(Rt, Rt2, Rn, offset, ls, type) \ argument
71 aarch64_insn_gen_load_store_pair(Rt, Rt2, Rn, offset, \
75 #define A64_PUSH(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, -16, STORE, PRE_INDEX) argument
77 #define A64_POP(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, 16, LOAD, POST_INDEX) argument
82 #define A64_LSX(sf, Rt, Rn, Rs, type) \ argument
83 aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
86 #define A64_LDXR(sf, Rt, Rn) \ argument
87 A64_LSX(sf, Rt, Rn, A64_ZR, LOAD_EX)
89 #define A64_STXR(sf, Rt, Rn, Rs) \ argument
90 A64_LSX(sf, Rt, Rn, Rs, STORE_EX)