Lines Matching refs:a6
917 btst &0x4,1+EXC_CMDREG(%a6) # is op an fsincos?
920 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
923 lea FP_DST(%a6),%a0 # pass: ptr to dst op
929 mov.b %d0,DTAG(%a6) # save dst optype tag
933 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6)
934 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6)
935 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6)
936 #$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6)
937 #$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6)
938 #$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6)
941 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode
943 mov.b 1+EXC_CMDREG(%a6),%d1
946 andi.l &0x00ff01ff,USER_FPSR(%a6)
951 lea FP_SRC(%a6),%a0
952 lea FP_DST(%a6),%a1
958 bfextu EXC_CMDREG(%a6){&6:&3},%d0
973 btst &unfl_bit,FPCR_ENABLE(%a6)
977 btst &inex2_bit,FPCR_ENABLE(%a6)
981 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
982 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
983 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
985 unlk %a6
1225 mov.l %a0,EXC_A7(%a6) # save on stack
1232 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
1233 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1234 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1236 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
1240 clr.b SPCOND_FLG(%a6) # clear special condition flag
1244 btst &0x5,EXC_CMDREG(%a6) # is it an fmove out?
1248 bfextu EXC_CMDREG(%a6){&0:&6},%d0
1269 lea FP_SRC(%a6),%a0 # pass: ptr to src op
1276 mov.b %d0,STAG(%a6) # save src optype tag
1278 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
1282 btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
1284 cmpi.b 1+EXC_CMDREG(%a6),&0x3a # is operation an ftst?
1323 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set
1328 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension
1333 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
1338 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1339 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1340 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1342 unlk %a6
1347 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled
1361 btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set?
1365 btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled?
1390 btst &unfl_bit,FPSR_EXCEPT(%a6) # did disabled underflow occur?
1392 btst &ovfl_bit,FPSR_EXCEPT(%a6) # did disabled overflow occur?
1403 mov.w (tbl_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) # create exc status
1405 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1406 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1407 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1409 frestore FP_SRC(%a6) # restore src op
1411 unlk %a6
1432 bfextu EXC_CMDREG(%a6){&0:&6},%d0 # extract opclass,src fmt
1500 bfextu EXC_CMDREG(%a6){&3:&3},%d0
1510 and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field
1521 lea FP_SRC(%a6),%a0
1524 mov.b %d0,STAG(%a6)
1528 mov.b &DENORM,STAG(%a6)
1532 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1534 lea FP_SRC(%a6),%a0 # pass ptr to src operand
1536 mov.l (%a6),EXC_A6(%a6) # in case a6 changes
1563 btst &0x5,EXC_SR(%a6)
1566 mov.l EXC_A7(%a6),%a0 # restore a7
1570 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1571 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1572 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1574 unlk %a6
1584 cmpi.b SPCOND_FLG(%a6),&mda7_flg
1677 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1678 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1679 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1681 mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd8
1682 mov.w &0xe006,2+FP_SRC(%a6)
1684 frestore FP_SRC(%a6)
1686 unlk %a6
1692 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1693 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1694 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1696 mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0
1697 mov.w &0xe004,2+FP_SRC(%a6)
1699 frestore FP_SRC(%a6)
1701 unlk %a6
1707 fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack
1709 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1710 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1711 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1713 mov.w &0x30d4,EXC_VOFF(%a6) # vector offset = 0xd4
1714 mov.w &0xe005,2+FP_SRC(%a6)
1716 frestore FP_SRC(%a6) # restore EXOP
1718 unlk %a6
1759 fmovm.x &0x80,FP_SRC(%a6) # put answer on stack
1760 fmovm.x &0x40,FP_DST(%a6) # put EXOP on stack
1762 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1763 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1764 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1766 mov.w &0x30cc,EXC_VOFF(%a6) # vector offset = 0xcc
1767 mov.w &0xe003,2+FP_DST(%a6)
1769 frestore FP_DST(%a6) # restore EXOP
1771 mov.l (%a6),%a6 # restore frame pointer
1788 fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack
1790 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1791 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1792 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1794 mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4
1795 mov.w &0xe001,2+FP_SRC(%a6)
1797 frestore FP_SRC(%a6) # restore EXOP
1799 unlk %a6
1834 lea FP_DST(%a6),%a0 # pass: ptr to dst op
1840 mov.b %d0,DTAG(%a6) # save dst optype tag
1844 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1846 bfextu 1+EXC_CMDREG(%a6){&1:&7},%d1 # extract extension
1848 lea FP_SRC(%a6),%a0
1849 lea FP_DST(%a6),%a1
1868 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
1873 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension
1878 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
1883 btst &0x5,EXC_SR(%a6) # user or supervisor?
1886 mov.l EXC_A7(%a6),%a0 # update user a7
1890 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1891 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1892 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1894 unlk %a6 # unravel stack frame
1925 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled & set
1939 btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set?
1943 btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled?
1968 btst &unfl_bit,FPSR_EXCEPT(%a6) # did disabled underflow occur?
1970 btst &ovfl_bit,FPSR_EXCEPT(%a6) # did disabled overflow occur?
1980 btst &0x5,EXC_SR(%a6) # user or supervisor?
1983 mov.l EXC_A7(%a6),%a0 # update user a7
1987 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6)
1989 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1990 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1991 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1993 frestore FP_SRC(%a6) # restore src op
1995 unlk %a6
2015 btst &mia7_bit,SPCOND_FLG(%a6)
2018 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6)
2020 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
2021 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2022 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2024 frestore FP_SRC(%a6) # restore src op
2026 unlk %a6 # unravel stack frame
2069 and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field
2074 bfextu EXC_CMDREG(%a6){&6:&3},%d0
2079 lea FP_SRC(%a6),%a0
2086 mov.b %d0,STAG(%a6) # save src optype tag
2089 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
2091 lea FP_SRC(%a6),%a0 # pass ptr to src operand
2093 mov.l (%a6),EXC_A6(%a6) # in case a6 changes
2108 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
2112 mov.l EXC_A6(%a6),(%a6) # restore a6
2114 btst &0x5,EXC_SR(%a6) # user or supervisor?
2117 mov.l EXC_A7(%a6),%a0 # update user a7
2121 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
2122 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2123 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2125 unlk %a6 # unravel stack frame
2303 bfextu EXC_EXTWORD(%a6){&3:&3},%d0 # extract src specifier
2311 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent
2318 mov.l FP_SRC_HI(%a6),%d1 # fetch DENORM hi(man)
2321 mov.l %d1,FP_SRC_HI(%a6) # insert new hi(man)
2322 andi.w &0x8000,FP_SRC_EX(%a6) # clear old exponent
2323 ori.w &0x3f80,FP_SRC_EX(%a6) # insert new "skewed" exponent
2328 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent
2334 tst.b FP_SRC_EX(%a6) # make "internal format"
2335 smi.b 0x2+FP_SRC(%a6)
2336 mov.w %d0,FP_SRC_EX(%a6) # insert exponent with cleared sign
2338 lea FP_SRC(%a6),%a0 # pass ptr to src op
2342 tst.b 0x2+FP_SRC(%a6) # is sign set?
2346 bset &0x7,FP_SRC_HI(%a6) # set j-bit
2347 mov.w %d0,FP_SRC_EX(%a6) # insert new exponent
2354 btst &0x5,EXC_SR(%a6)
2356 mov.l 0x0(%a0),FP_DST_EX(%a6)
2357 mov.l 0x4(%a0),FP_DST_HI(%a6)
2358 mov.l 0x8(%a0),FP_DST_LO(%a6)
2464 link %a6,&-LOCAL_SIZE # init stack frame
2466 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
2467 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
2468 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
2471 mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6)
2473 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
2474 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
2476 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
2536 mov.b 3+FP_SRC(%a6),%d0 # get byte 4
2539 tst.l FP_SRC_HI(%a6) # is lw 2 zero?
2541 tst.l FP_SRC_LO(%a6) # is lw 3 zero?
2544 lea FP_SRC(%a6),%a0 # pass: ptr to packed op
2546 fmovm.x &0x80,FP_SRC(%a6) # make this the srcop
2549 addi.l &0xc,EXC_EXTWPTR(%a6) # update extension word pointer
2552 lea FP_SRC(%a6),%a0 # pass: ptr to src op
2554 mov.b %d0,STAG(%a6) # could be ANYTHING!!!
2558 mov.b %d0,STAG(%a6) # set new optype tag
2560 clr.b STORE_FLG(%a6) # clear "store result" boolean
2562 btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
2564 btst &0x4,1+EXC_CMDREG(%a6) # is operation fsincos,ftst,fcmp?
2568 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch dst regno
2571 lea FP_DST(%a6),%a0 # pass: ptr to dst op
2573 mov.b %d0,DTAG(%a6) # could be ANYTHING!!!
2577 mov.b %d0,DTAG(%a6) # set new optype tag
2582 btst &0x3,1+EXC_CMDREG(%a6) # is operation fsincos?
2587 btst &0x1,1+EXC_CMDREG(%a6) # is operation fcmp?
2592 mov.b FPCR_MODE(%a6),%d0 # pass: rnd mode,prec
2594 mov.b 1+EXC_CMDREG(%a6),%d1
2600 lea FP_SRC(%a6),%a0
2601 lea FP_DST(%a6),%a1
2620 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
2930 # -restore a6 (not with unlk)
2931 # -shift stack frame down over where old a6 used to be
2934 mov.l (%a6),%a6 # restore frame pointer
2953 link %a6,&-LOCAL_SIZE # init stack frame
2955 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
2958 mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6)
2959 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
2960 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
2962 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
2988 mov.l EXC_EXTWPTR(%a6),%d0
2989 sub.l EXC_PC(%a6),%d0
2991 mov.w %d0,EXC_VOFF(%a6) # store stack shift value
2993 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2995 unlk %a6
3019 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3020 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 on stack
3022 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3024 unlk %a6
3042 lea -LOCAL_SIZE(%a6),%sp
3047 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 on stack
3050 mov.l (%a6),%a6
3167 mov.w FP_SRC_EX(%a6),%d1 # fetch exponent
3172 tst.l FP_SRC_LO(%a6)
3174 mov.l FP_SRC_HI(%a6),%d1
3178 mov.l FP_SRC_HI(%a6),L_SCR1(%a6)
3183 tst.b FP_SRC_EX(%a6)
3187 mov.l %d1,L_SCR1(%a6)
3191 mov.b 1+EXC_OPWORD(%a6),%d1 # extract <ea> mode,reg
3305 link.w %a6,&-LOCAL_SIZE # init stack frame
3307 fsave FP_SRC(%a6) # grab the "busy" frame
3309 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3310 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
3311 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
3314 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
3316 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
3317 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
3319 mov.l %d0,EXC_OPWORD(%a6)
3331 lea FP_SRC(%a6),%a0 # pass: ptr to src op
3335 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3336 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3337 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3339 frestore FP_SRC(%a6)
3341 unlk %a6
3361 mov.b 1+EXC_OPWORD(%a6),%d1 # extract <ea> mode,reg
3725 mov.b &NORM,STAG(%a6) # src is a NORM
3728 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode
3730 andi.l &0xffff00ff,USER_FPSR(%a6) # zero exception field
3732 lea FP_SRC(%a6),%a0 # pass ptr to src operand
3771 link.w %a6,&-LOCAL_SIZE # init stack frame
3773 fsave FP_SRC(%a6) # grab the "busy" frame
3775 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3776 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
3777 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
3780 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
3782 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
3783 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
3785 mov.l %d0,EXC_OPWORD(%a6)
3793 lea FP_SRC(%a6),%a0 # pass: ptr to src op
3797 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3798 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3799 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3801 frestore FP_SRC(%a6)
3803 unlk %a6
3861 link.w %a6,&-LOCAL_SIZE # init stack frame
3863 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3865 mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6)
3866 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
3867 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
4038 mov.l %a0,EXC_A7(%a6) # store a7'
4070 clr.b STORE_FLG(%a6) # clear "store result" flag
4073 andi.l &0x00ff00ff,USER_FPSR(%a6)
4083 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode
4085 mov.b 1+EXC_CMDREG(%a6),%d1
4088 or.b STAG(%a6),%d1 # insert src optag bits
4090 lea FP_DST(%a6),%a1 # pass dst ptr in a1
4091 lea FP_SRC(%a6),%a0 # pass src ptr in a0
4097 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
4101 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch Dn
4105 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
4106 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
4107 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
4110 cmpi.b SPCOND_FLG(%a6),&mia7_flg # was the ea mode (sp)+ ?
4113 cmpi.b SPCOND_FLG(%a6),&mda7_flg # was the ea mode -(sp) ?
4117 unlk %a6
4150 sub.l OLD_A7(%a6),%d0 # subtract old a7'
4181 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled and set
4222 mov.w (tbl_funimp_except.b,%pc,%d0.w*2),2+FP_SRC(%a6)
4232 mov.w &0xe005,2+FP_SRC(%a6)
4238 mov.w &0xe003,2+FP_SRC(%a6)
4243 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
4244 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
4245 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
4247 frestore FP_SRC(%a6) # insert exceptional status
4359 cmpi.b SPCOND_FLG(%a6),&mda7_flg # was a7 modified?
4362 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
4363 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
4364 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
4366 unlk %a6
4404 mov.w &0x00c0,2+EXC_EA(%a6) # Fmt = 0x0; Vector Offset = 0x0c0
4405 mov.l USER_FPIAR(%a6),EXC_VOFF(%a6) # PC = Current PC
4406 mov.w EXC_SR(%a6),2+EXC_PC(%a6) # shift SR "up"
4408 mov.w &0xe000,2+FP_SRC(%a6) # bsun exception enabled
4410 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
4411 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
4412 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
4414 frestore FP_SRC(%a6) # restore bsun exception
4416 unlk %a6
5191 fmov.x %fp0,X(%a6) # X IS R
5203 eor.l %d1,X(%a6) # X IS NOW R'= SGN*R
5230 fadd.x X(%a6),%fp0 # last inst - possible exception set
5266 mov.l %d1,POSNEG1(%a6)
5287 fmul.x X(%a6),%fp0
5292 fadd.s POSNEG1(%a6),%fp0 # last inst - possible exception set
5305 mov.l ADJN(%a6),%d1
5312 # mov.w &0x0000,XDCARE(%a6) # JUST IN CASE
5316 fmov.x X(%a6),%fp0 # last inst - possible exception set
5343 mov.l &4,ADJN(%a6)
5346 fmov.x %fp0,X(%a6)
5371 fmov.l %fp1,INT(%a6) # CONVERT TO INTEGER
5373 mov.l INT(%a6),%d1
5383 mov.l INT(%a6),%d1
5392 fmov.x %fp0,RPRIME(%a6)
5410 eor.l %d2,RPRIME(%a6)
5415 mov.l &0x3F800000,POSNEG1(%a6)
5416 eor.l %d1,POSNEG1(%a6)
5423 fmov.x %fp0,SPRIME(%a6)
5426 eor.l %d1,SPRIME(%a6)
5450 fmul.x RPRIME(%a6),%fp1 # R'S(A1+...)
5457 fadd.x RPRIME(%a6),%fp1 # COS(X)
5459 fadd.s POSNEG1(%a6),%fp0 # SIN(X)
5466 fmov.x %fp0,RPRIME(%a6)
5473 fmov.x %fp0,SPRIME(%a6)
5482 eor.l %d1,RPRIME(%a6)
5483 eor.l %d1,SPRIME(%a6)
5488 mov.l %d1,POSNEG1(%a6)
5524 fmul.x RPRIME(%a6),%fp0 # R'S(A1+...)
5530 fadd.s POSNEG1(%a6),%fp1 # COS(X)
5532 fadd.x RPRIME(%a6),%fp0 # SIN(X)
5544 # mov.w &0x0000,XDCARE(%a6)
5552 fmov.x X(%a6),%fp0
5584 mov.w &0x7ffe,FP_SCR0_EX(%a6)
5585 mov.l &0xc90fdaa2,FP_SCR0_HI(%a6)
5586 clr.l FP_SCR0_LO(%a6)
5589 mov.w &0x7fdc,FP_SCR1_EX(%a6)
5590 mov.l &0x85a308d3,FP_SCR1_HI(%a6)
5591 clr.l FP_SCR1_LO(%a6)
5596 or.b &0x80,FP_SCR0_EX(%a6) # positive arg
5597 or.b &0x80,FP_SCR1_EX(%a6)
5599 fadd.x FP_SCR0(%a6),%fp0 # high part of reduction is exact
5601 fadd.x FP_SCR1(%a6),%fp0 # low part of reduction
5603 fadd.x FP_SCR1(%a6),%fp1 # fp0/fp1 are reduced argument.
5609 fmov.x %fp0,INARG(%a6) # +-2**K * F, 1 <= F < 2
5610 mov.w INARG(%a6),%d1
5618 mov.b &0,ENDFLAG(%a6)
5622 mov.b &1,ENDFLAG(%a6)
5634 mov.l &0xA2F9836E,FP_SCR0_HI(%a6)
5635 mov.l &0x4E44152A,FP_SCR0_LO(%a6)
5636 mov.w %d2,FP_SCR0_EX(%a6) # FP_SCR0 = 2**(-L)*(2/PI)
5639 fmul.x FP_SCR0(%a6),%fp2 # fp2 = X * 2**(-L)*(2/PI)
6081 mov.l %d2,TWOTO63(%a6)
6082 fadd.s TWOTO63(%a6),%fp2 # THE FRACTIONAL PART OF FP1 IS ROUNDED
6083 fsub.s TWOTO63(%a6),%fp2 # fp2 = N
6090 mov.w %d2,FP_SCR0_EX(%a6)
6091 mov.l &0xC90FDAA2,FP_SCR0_HI(%a6)
6092 clr.l FP_SCR0_LO(%a6) # FP_SCR0 = 2**(L) * Piby2_1
6095 mov.w %d1,FP_SCR1_EX(%a6)
6096 mov.l &0x85A308D3,FP_SCR1_HI(%a6)
6097 clr.l FP_SCR1_LO(%a6) # FP_SCR1 = 2**(L) * Piby2_2
6099 mov.b ENDFLAG(%a6),%d1
6104 fmul.x FP_SCR0(%a6),%fp4 # fp4 = W = N*P1
6106 fmul.x FP_SCR1(%a6),%fp5 # fp5 = w = N*P2
6133 fmov.l %fp2,INT(%a6)
6137 mov.l INT(%a6),%d1
6387 and.l &0xF8000000,XFRAC(%a6) # FIRST 5 BITS
6388 or.l &0x04000000,XFRAC(%a6) # SET 6-TH BIT TO 1
6389 mov.l &0x00000000,XFRACLO(%a6) # LOCATION OF X IS NOW F
6392 fmul.x X(%a6),%fp1 # FP1 IS X*F, NOTE THAT X*F > 0
6393 fsub.x X(%a6),%fp0 # FP0 IS X-F
6446 fadd.x ATANF(%a6),%fp0 # ATAN(X)
6489 fmul.x X(%a6),%fp0 # X*Y
6498 fadd.x X(%a6),%fp0
6506 fmov.x X(%a6),%fp0 # last inst - possible exception set
6530 fmov.x %fp1,X(%a6) # X IS REALLY X'
7631 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
7640 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
7650 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy to tmp loc
7651 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy to tmp loc
7652 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent
7653 fmov.x FP_SCR0(%a6),%fp0 # put new value back in fp0
8451 fmov.x %fp1,SAVEU(%a6) # STORE U IN MEMORY, FREE FP1
8469 fmul.x SAVEU(%a6),%fp0 # FP0 IS U*V
8477 fadd.x SAVEU(%a6),%fp0
8488 mov.l &-100,ADJK(%a6) # INPUT = 2^(ADJK) * FP0
8513 mov.l %d3,X(%a6)
8514 mov.l %d4,XFRAC(%a6)
8515 mov.l %d5,XFRAC+4(%a6)
8517 mov.l %d2,ADJK(%a6)
8518 fmov.x X(%a6),%fp0
8520 lea X(%a6),%a0
8535 mov.l %d3,X(%a6)
8536 mov.l %d4,XFRAC(%a6)
8537 mov.l %d5,XFRAC+4(%a6)
8539 mov.l %d2,ADJK(%a6)
8540 fmov.x X(%a6),%fp0
8542 lea X(%a6),%a0
9451 ori.l &inx2a_mask,USER_FPSR(%a6) # set INEX2/AINEX
9470 mov.w 0x0(%a0,%d1.w),FP_SCR1_EX(%a6) # load first word
9471 mov.l 0x4(%a0,%d1.w),FP_SCR1_HI(%a6) # load second word
9472 mov.l 0x8(%a0,%d1.w),FP_SCR1_LO(%a6) # load third word
9475 lea FP_SCR1(%a6),%a0 # pass ptr to answer
9584 smi.b SIGN(%a6) # use SIGN to hold dst sign
10089 clr.b Sc_Flag(%a6)
10101 mov.w SignX(%a6),%d6
10103 mov.w %d6,SignX(%a6)
10138 ori.l &dzinf_mask,USER_FPSR(%a6) # set I/DZ/ADZ
10144 ori.l &dzinf_mask+neg_mask,USER_FPSR(%a6) # set N/I/DZ/ADZ
10154 ori.l &opnan_mask,USER_FPSR(%a6) # set NaN/OPERR/AIOP
10170 ori.l &unfl_mask,USER_FPSR(%a6) # set UNFL
10175 ori.l &unfinx_mask,USER_FPSR(%a6) # set UNFL/INEX2/AUNFL/AINEX
10187 bset &neg_bit,FPSR_CC(%a6) # yes; set 'N' ccode bit
10200 mov.b FPCR_ENABLE(%a6),%d0
10212 mov.w LOCAL_EX(%a1),FP_SCR0_EX(%a6)
10213 mov.l LOCAL_HI(%a1),FP_SCR0_HI(%a6)
10214 mov.l LOCAL_LO(%a1),FP_SCR0_LO(%a6)
10216 lea FP_SCR0(%a6),%a0
10219 andi.w &0x8000,FP_SCR0_EX(%a6) # keep old sign
10220 or.w %d0,FP_SCR0_EX(%a6) # insert new exponent
10222 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
10276 ori.l &ovfl_inx_mask,USER_FPSR(%a6) # set OVFL/AOVFL/AINEX
11365 mov.b &NORM,STAG(%a6)
11368 mov.b &NORM,DTAG(%a6)
11378 fmovm.x &0x80,FP_DST(%a6) # dst op is in fp0
11381 lea FP_DST(%a6),%a1 # pass: ptr to dst op
11398 mov.b &DENORM,STAG(%a6)
11623 fmovm.x FP_SCR1(%a6),&0x80 # load dst operand
11625 fmov.l L_SCR3(%a6),%fpcr # set FPCR
11628 fmul.x FP_SCR0(%a6),%fp0 # execute multiply
11633 or.l %d1,USER_FPSR(%a6) # save INEX2,N
11636 fmovm.x &0x80,FP_SCR0(%a6) # store out result
11638 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
11644 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
11646 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
11663 fmovm.x FP_SCR1(%a6),&0x80 # load dst operand
11665 fmov.l L_SCR3(%a6),%fpcr # set FPCR
11668 fmul.x FP_SCR0(%a6),%fp0 # execute multiply
11673 or.l %d1,USER_FPSR(%a6) # save INEX2,N
11677 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
11679 mov.b FPCR_ENABLE(%a6),%d1
11685 btst &neg_bit,FPSR_CC(%a6) # is result negative?
11687 mov.l L_SCR3(%a6),%d0 # pass rnd prec,mode
11689 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
11700 mov.l L_SCR3(%a6),%d1
11774 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
12001 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set INF/N
12005 mov.b &inf_bmask,FPSR_CC(%a6) # set INF
12280 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
12288 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
12290 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
12298 fmov.l L_SCR3(%a6),%fpcr # set FPCR
12300 fmov.x FP_SCR0(%a6),%fp0 # perform the move
12305 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12335 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes
13060 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
13068 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
13069 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
13078 fmov.l L_SCR3(%a6),%fpcr # set FPCR
13080 fneg.x FP_SCR0(%a6),%fp0 # perform negation
13085 or.l %d1,USER_FPSR(%a6) # save INEX2,N
13115 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes
13139 mov.b STAG(%a6),%d1
13150 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
13174 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
13184 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit
13187 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'I','N' ccode bits
13197 mov.b &z_bmask,FPSR_CC(%a6) # set 'N' ccode bit
13200 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits
13337 mov.b STAG(%a6),%d1
13349 or.l %d0,USER_FPSR(%a6) # set exception bits
13377 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) # copy sign, zero exp
13378 mov.b &0x80,FP_SCR0_HI(%a6) # force DENORM ==> small NORM
13379 lea FP_SCR0(%a6),%a0
13390 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
13394 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits
13405 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit
13408 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits
13461 mov.l %d0,L_SCR3(%a6) # store rnd info
13462 mov.b STAG(%a6),%d1
13477 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
13478 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
13481 mov.w %d1,FP_SCR0_EX(%a6) # insert exponent
13482 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
13493 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
13495 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
13496 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
13499 mov.w %d0,FP_SCR0_EX(%a6) # insert exponent
13501 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
13503 btst &unfl_bit,FPCR_ENABLE(%a6) # is UNFL enabled?
13513 lea FP_SCR0(%a6),%a0 # pass: ptr to operand
13517 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp
13521 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent
13522 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
13536 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
13537 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
13538 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
13552 fmov.l L_SCR3(%a6),%fpcr # set FPCR
13554 fabs.x FP_SCR0(%a6),%fp0 # perform absolute
13559 or.l %d1,USER_FPSR(%a6) # save INEX2,N
13563 fmovm.x &0x80,FP_SCR0(%a6) # store out result
13564 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp
13570 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent
13572 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
13579 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
13580 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
13581 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
13595 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
13597 bclr &0x7,FP_SCR0_EX(%a6) # force absolute value
13600 mov.b FPCR_ENABLE(%a6),%d1
13605 lea FP_SCR0(%a6),%a0 # pass: result addr
13606 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
13608 or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode
13609 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
13617 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
13618 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6)
13619 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent
13629 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp
13630 fmovm.x FP_SCR1(%a6),&0x40 # return EXOP in fp1
13639 fmov.l L_SCR3(%a6),%fpcr # set FPCR
13641 fabs.x FP_SCR0(%a6),%fp0 # perform absolute
13646 or.l %d1,USER_FPSR(%a6) # save INEX2,N
13649 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
13651 mov.b FPCR_ENABLE(%a6),%d1
13660 btst &neg_bit,FPSR_CC(%a6) # is result negative?
13662 mov.l L_SCR3(%a6),%d0 # pass: prec,mode
13664 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
13727 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
13730 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit
13759 mov.b DTAG(%a6),%d1
13761 or.b STAG(%a6),%d1
13774 mov.b %d0,FPSR_CC(%a6) # set ccode bits(no exc bits are set)
13845 andi.b &0xf7,FPSR_CC(%a6)
13849 andi.b &0xf7,FPSR_CC(%a6)
13960 mov.l %d0,L_SCR3(%a6) # store rnd info
13963 mov.b DTAG(%a6),%d1
13965 or.b STAG(%a6),%d1
13970 mov.w DST_EX(%a1),FP_SCR1_EX(%a6)
13971 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
13972 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
13974 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
13975 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
13976 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
13994 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
13996 fmov.l L_SCR3(%a6),%fpcr # set FPCR
13999 fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
14004 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14007 fmovm.x &0x80,FP_SCR0(%a6) # store out result
14009 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
14015 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14017 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
14021 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14023 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14026 fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
14031 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14036 or.l &ovfl_inx_mask, USER_FPSR(%a6) # set ovfl/aovfl/ainex
14038 mov.b FPCR_ENABLE(%a6),%d1
14043 btst &neg_bit,FPSR_CC(%a6) # is result negative?
14045 mov.l L_SCR3(%a6),%d0 # pass prec:rnd
14048 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
14053 fmovm.x &0x80,FP_SCR0(%a6) # move result to stack
14056 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
14064 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14066 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
14070 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14072 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14075 fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
14080 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14301 mov.l %d0,L_SCR3(%a6) # store rnd info
14304 mov.b DTAG(%a6),%d1
14306 or.b STAG(%a6),%d1 # combine src tags
14314 mov.w DST_EX(%a1),FP_SCR1_EX(%a6)
14315 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
14316 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
14318 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
14319 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
14320 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
14330 mov.w 2+L_SCR3(%a6),%d1 # fetch precision,mode
14341 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14343 fmov.l L_SCR3(%a6),%fpcr # save FPCR
14346 fsgldiv.x FP_SCR0(%a6),%fp0 # perform sgl divide
14351 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14354 fmovm.x &0x80,FP_SCR0(%a6) # store result on stack
14356 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
14362 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14364 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
14368 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14370 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14373 fsgldiv.x FP_SCR0(%a6),%fp0 # execute divide
14378 or.l %d1,USER_FPSR(%a6) # save INEX,N
14389 or.w &ovfl_inx_mask,2+USER_FPSR(%a6) # set ovfl/aovfl/ainex
14391 mov.b FPCR_ENABLE(%a6),%d1
14396 btst &neg_bit,FPSR_CC(%a6) # is result negative
14398 mov.l L_SCR3(%a6),%d0 # pass prec:rnd
14401 or.b %d0,FPSR_CC(%a6) # set INF if applicable
14406 fmovm.x &0x80,FP_SCR0(%a6) # move result to stack
14409 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
14417 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14419 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
14423 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
14425 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14430 fsgldiv.x FP_SCR0(%a6),%fp0 # execute sgl divide
14435 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14437 mov.b FPCR_ENABLE(%a6),%d1
14442 fmovm.x &0x80,FP_SCR0(%a6) # store out result
14444 lea FP_SCR0(%a6),%a0 # pass: result addr
14445 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
14447 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set
14448 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
14455 fmovm.x FP_SCR1(%a6),&0x40 # load dst op
14457 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14460 fsgldiv.x FP_SCR0(%a6),%fp1 # execute sgl divide
14464 fmovm.x &0x40,FP_SCR0(%a6) # save result to stack
14466 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
14474 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14476 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
14483 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14485 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14488 fsgldiv.x FP_SCR0(%a6),%fp0 # execute sgl divide
14493 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14507 fmovm.x FP_SCR1(%a6),&0x40 # load dst op into %fp1
14515 fsgldiv.x FP_SCR0(%a6),%fp1 # execute sgl divide
14648 mov.l %d0,L_SCR3(%a6) # store rnd info
14651 mov.b DTAG(%a6),%d1
14653 or.b STAG(%a6),%d1 # combine src tags
14664 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14667 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14669 fadd.x FP_SCR0(%a6),%fp0 # execute add
14674 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
14682 mov.w 2+L_SCR3(%a6),%d1
14722 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
14724 mov.b FPCR_ENABLE(%a6),%d1
14730 btst &neg_bit,FPSR_CC(%a6) # is result negative?
14732 mov.l L_SCR3(%a6),%d0 # pass prec:rnd
14734 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
14740 mov.b L_SCR3(%a6),%d1
14756 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14758 mov.l L_SCR3(%a6),%d1
14762 fadd.x FP_SCR0(%a6),%fp0 # execute add
14771 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
14775 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14780 fadd.x FP_SCR0(%a6),%fp0 # execute add
14785 or.l %d1,USER_FPSR(%a6) # save INEX,N
14787 mov.b FPCR_ENABLE(%a6),%d1
14792 fmovm.x &0x80,FP_SCR0(%a6) # store out result
14794 lea FP_SCR0(%a6),%a0 # pass: result addr
14795 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
14797 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set
14798 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
14803 fmovm.x FP_SCR1(%a6),&0x40 # load dst op
14805 mov.l L_SCR3(%a6),%d1
14809 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14814 fadd.x FP_SCR0(%a6),%fp1 # execute multiply
14818 fmovm.x &0x40,FP_SCR0(%a6) # save result to stack
14819 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
14827 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14828 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
14832 mov.l L_SCR3(%a6),%d1
14844 mov.l L_SCR3(%a6),%d1
14855 btst &inex2_bit,FPSR_EXCEPT(%a6) # is INEX2 set?
14868 fmovm.x FP_SCR1(%a6),&0x40 # load dst op into fp1
14870 mov.l L_SCR3(%a6),%d1
14876 fadd.x FP_SCR0(%a6),%fp1 # execute add
14971 mov.b &z_bmask,FPSR_CC(%a6) # set Z
14980 mov.b 3+L_SCR3(%a6),%d1
14985 mov.b &z_bmask,FPSR_CC(%a6) # set Z
14990 mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set NEG/Z
14998 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
14999 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
15000 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
15002 clr.w FP_SCR1_EX(%a6)
15003 clr.l FP_SCR1_HI(%a6)
15004 clr.l FP_SCR1_LO(%a6)
15008 mov.w DST_EX(%a1),FP_SCR1_EX(%a6)
15009 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
15010 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
15012 clr.w FP_SCR0_EX(%a6)
15013 clr.l FP_SCR0_HI(%a6)
15014 clr.l FP_SCR0_LO(%a6)
15047 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG
15051 mov.b &inf_bmask,FPSR_CC(%a6) # set INF
15101 mov.l %d0,L_SCR3(%a6) # store rnd info
15104 mov.b DTAG(%a6),%d1
15106 or.b STAG(%a6),%d1 # combine src tags
15117 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
15120 fmov.l L_SCR3(%a6),%fpcr # set FPCR
15122 fsub.x FP_SCR0(%a6),%fp0 # execute subtract
15127 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
15135 mov.w 2+L_SCR3(%a6),%d1
15175 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
15177 mov.b FPCR_ENABLE(%a6),%d1
15183 btst &neg_bit,FPSR_CC(%a6) # is result negative?
15185 mov.l L_SCR3(%a6),%d0 # pass prec:rnd
15187 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
15193 mov.b L_SCR3(%a6),%d1
15209 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
15211 mov.l L_SCR3(%a6),%d1
15215 fsub.x FP_SCR0(%a6),%fp0 # execute subtract
15224 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
15228 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
15233 fsub.x FP_SCR0(%a6),%fp0 # execute subtract
15238 or.l %d1,USER_FPSR(%a6)
15240 mov.b FPCR_ENABLE(%a6),%d1
15245 fmovm.x &0x80,FP_SCR0(%a6) # store out result
15247 lea FP_SCR0(%a6),%a0 # pass: result addr
15248 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
15250 or.b %d0,FPSR_CC(%a6) # 'Z' may have been set
15251 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
15256 fmovm.x FP_SCR1(%a6),&0x40
15258 mov.l L_SCR3(%a6),%d1
15262 fmov.l L_SCR3(%a6),%fpcr # set FPCR
15267 fsub.x FP_SCR0(%a6),%fp1 # execute subtract
15271 fmovm.x &0x40,FP_SCR0(%a6) # store result to stack
15272 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
15280 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
15281 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
15285 mov.l L_SCR3(%a6),%d1
15297 mov.l L_SCR3(%a6),%d1
15308 btst &inex2_bit,FPSR_EXCEPT(%a6) # is INEX2 set?
15321 fmovm.x FP_SCR1(%a6),&0x40 # load dst op into fp1
15323 mov.l L_SCR3(%a6),%d1
15329 fsub.x FP_SCR0(%a6),%fp1 # execute subtract
15423 mov.b &z_bmask,FPSR_CC(%a6) # set Z
15432 mov.b 3+L_SCR3(%a6),%d1
15437 mov.b &z_bmask,FPSR_CC(%a6) # set Z
15442 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set Z/NEG
15450 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
15451 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
15452 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
15454 clr.w FP_SCR1_EX(%a6)
15455 clr.l FP_SCR1_HI(%a6)
15456 clr.l FP_SCR1_LO(%a6)
15460 mov.w DST_EX(%a1),FP_SCR1_EX(%a6)
15461 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
15462 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
15464 clr.w FP_SCR0_EX(%a6)
15465 clr.l FP_SCR0_HI(%a6)
15466 clr.l FP_SCR0_LO(%a6)
15486 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG
15493 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG
15497 mov.b &inf_bmask,FPSR_CC(%a6) # set INF
15660 btst &0x0,1+FP_SCR0_EX(%a6) # is exponent 0x3fff?
15667 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
15672 fsqrt.x FP_SCR0(%a6),%fp0 # execute square root
15677 or.l %d1,USER_FPSR(%a6) # save INEX2,N
15680 mov.b FPCR_ENABLE(%a6),%d1
15685 fmovm.x &0x80,FP_SCR0(%a6) # store out result
15687 lea FP_SCR0(%a6),%a0 # pass: result addr
15688 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
15690 or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode
15691 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
15699 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
15700 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6)
15701 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent
15711 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp
15712 fmovm.x FP_SCR1(%a6),&0x40 # return EXOP in fp1
15721 fmov.l L_SCR3(%a6),%fpcr # set FPCR
15723 fsqrt.x FP_SCR0(%a6),%fp0 # perform square root
15728 or.l %d1,USER_FPSR(%a6) # save INEX2,N
15731 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
15733 mov.b FPCR_ENABLE(%a6),%d1
15742 btst &neg_bit,FPSR_CC(%a6) # is result negative?
15744 mov.l L_SCR3(%a6),%d0 # pass: prec,mode
15746 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
15821 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
15825 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits
15833 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit
15847 # FP_SRC(a6) = fp op1(src) #
15848 # FP_DST(a6) = fp op2(dst) #
15851 # FP_SRC(a6) = fp op1 scaled(src) #
15852 # FP_DST(a6) = fp op2 scaled(dst) #
15868 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
15869 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
15870 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
15871 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
15874 mov.w %d0,FP_SCR0_EX(%a6)
15875 mov.w %d1,FP_SCR1_EX(%a6)
15879 mov.w %d0,L_SCR1(%a6) # store src exponent
15880 mov.w %d1,2+L_SCR1(%a6) # store dst exponent
15890 cmpi.b STAG(%a6),&DENORM # is dst denormalized?
15893 lea FP_SCR0(%a6),%a0
15896 mov.w %d0,L_SCR1(%a6) # inset new exp
15899 mov.w 2+L_SCR1(%a6),%d0
15902 cmp.w %d0,L_SCR1(%a6) # is difference >= len(mantissa)+2?
15905 mov.w L_SCR1(%a6),%d0
15907 mov.w FP_SCR0_EX(%a6),%d1
15910 mov.w %d0,FP_SCR0_EX(%a6) # insert new dst exponent
15916 andi.w &0x8000,FP_SCR0_EX(%a6) # zero src exponent
15917 bset &0x0,1+FP_SCR0_EX(%a6) # set exp = 1
15927 cmpi.b DTAG(%a6),&DENORM # is dst denormalized?
15929 lea FP_SCR1(%a6),%a0
15932 mov.w %d0,2+L_SCR1(%a6) # inset new exp
15935 mov.w L_SCR1(%a6),%d0
15938 cmp.w %d0,2+L_SCR1(%a6) # is difference >= len(mantissa)+2?
15941 mov.w 2+L_SCR1(%a6),%d0
15943 mov.w FP_SCR1_EX(%a6),%d1
15946 mov.w %d0,FP_SCR1_EX(%a6) # insert new dst exponent
15952 andi.w &0x8000,FP_SCR1_EX(%a6) # zero dst exponent
15953 bset &0x0,1+FP_SCR1_EX(%a6) # set exp = 1
15963 # value at FP_SCR0(a6). #
15969 # FP_SCR0(a6) = extended precision operand to be scaled #
15972 # FP_SCR0(a6) = scaled extended precision operand #
15985 mov.w FP_SCR0_EX(%a6),%d1 # extract operand's {sgn,exp}
15993 mov.w %d0,FP_SCR0_EX(%a6) # insert biased exponent
15995 cmpi.b STAG(%a6),&DENORM # is operand normalized?
16005 lea FP_SCR0(%a6),%a0 # pass ptr to src op
16050 ori.w &0x3fff,FP_SCR0_EX(%a6) # insert new operand's exponent(=0)
16066 lea FP_SCR0(%a6),%a0 # pass ptr to src op
16072 ori.w &0x3fff,FP_SCR0_EX(%a6) # insert new operand's exponent(=0)
16090 # value at FP_SCR1(a6). #
16096 # FP_SCR1(a6) = extended precision operand to be scaled #
16099 # FP_SCR1(a6) = scaled extended precision operand #
16112 mov.w FP_SCR1_EX(%a6),%d1 # extract operand's {sgn,exp}
16120 mov.w %d0,FP_SCR1_EX(%a6) # insert biased exponent
16122 cmpi.b DTAG(%a6),&DENORM # is operand normalized?
16131 lea FP_SCR1(%a6),%a0 # pass ptr to dst op
16150 # FP_SRC(a6) = pointer to extended precision src operand #
16151 # FP_DST(a6) = pointer to extended precision dst operand #
16176 cmp.b DTAG(%a6), &SNAN # is the dst an SNAN?
16178 cmp.b DTAG(%a6), &QNAN # is the dst a QNAN?
16181 cmp.b STAG(%a6), &QNAN
16186 bset &0x6, FP_SRC_HI(%a6) # set SNAN bit
16187 or.l &nan_mask+aiop_mask+snan_mask, USER_FPSR(%a6)
16188 lea FP_SRC(%a6), %a0
16193 or.l &nan_mask, USER_FPSR(%a6)
16194 lea FP_SRC(%a6), %a0
16197 or.l &nan_mask+aiop_mask+snan_mask, USER_FPSR(%a6)
16198 bset &0x6, FP_DST_HI(%a6) # set SNAN bit
16199 lea FP_DST(%a6), %a0
16202 lea FP_DST(%a6), %a0
16203 cmp.b STAG(%a6), &SNAN
16205 or.l &aiop_mask+snan_mask, USER_FPSR(%a6)
16207 or.l &nan_mask, USER_FPSR(%a6)
16211 or.l &neg_mask, USER_FPSR(%a6)
16240 or.l &nan_mask+operr_mask+aiop_mask, USER_FPSR(%a6)
16280 mov.l %d0,L_SCR1(%a6) # save displacement
16282 mov.w EXC_CMDREG(%a6),%d0 # fetch predicate
16285 mov.b FPSR_CC(%a6),%d1 # fetch fp ccodes
16375 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16377 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16378 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16394 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16396 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16397 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16410 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16412 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16413 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16417 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16419 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16420 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16435 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16437 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16438 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16451 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16453 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16454 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16470 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16472 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16473 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16486 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16488 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16489 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16493 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16495 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16496 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16511 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16513 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16514 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16527 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16529 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16530 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16546 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16548 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16549 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16562 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16563 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16579 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16580 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16614 btst &nan_bit, FPSR_CC(%a6) # is NAN set?
16616 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16617 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16627 btst &nan_bit, FPSR_CC(%a6) # is NAN set?
16629 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16630 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16643 btst &nan_bit, FPSR_CC(%a6) # is NAN set?
16645 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16646 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16650 btst &nan_bit, FPSR_CC(%a6) # is NAN set?
16652 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16653 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16666 btst &nan_bit, FPSR_CC(%a6) # is NAN set?
16668 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16669 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16673 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
16675 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16676 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16848 mov.b 1+EXC_OPWORD(%a6), %d1 # fetch lo opword
18052 btst &bsun_bit,FPCR_ENABLE(%a6) # was BSUN set?
18064 mov.b 1+EXC_OPWORD(%a6),%d1 # fetch lo opword
18103 mov.l EXC_EA(%a6),%a0 # fetch <ea>
18109 mov.b 0x1+EXC_OPWORD(%a6),%d1 # fetch opword
18240 btst &0x5,EXC_EXTWORD(%a6) # is it a move in or out?
18279 mov.l 0x0+EXC_FP0(%a6),(%a0)+ # yes
18280 mov.l 0x4+EXC_FP0(%a6),(%a0)+
18281 mov.l 0x8+EXC_FP0(%a6),(%a0)+
18287 mov.l 0x0+EXC_FP1(%a6),(%a0)+ # yes
18288 mov.l 0x4+EXC_FP1(%a6),(%a0)+
18289 mov.l 0x8+EXC_FP1(%a6),(%a0)+
18334 mov.l %a1,L_SCR1(%a6)
18352 mov.l %a0,L_SCR1(%a6)
18374 mov.l (%a0)+,0x0+EXC_FP0(%a6) # yes
18375 mov.l (%a0)+,0x4+EXC_FP0(%a6)
18376 mov.l (%a0)+,0x8+EXC_FP0(%a6)
18382 mov.l (%a0)+,0x0+EXC_FP1(%a6) # yes
18383 mov.l (%a0)+,0x4+EXC_FP1(%a6)
18384 mov.l (%a0)+,0x8+EXC_FP1(%a6)
18528 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word
18616 mov.l EXC_DREGS+0x8(%a6),%a0 # Get current a0
18620 mov.l EXC_DREGS+0xc(%a6),%a0 # Get current a1
18640 mov.l (%a6),%a0 # Get current a6
18644 mov.l EXC_A7(%a6),%a0 # Get current a7
18651 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0
18654 mov.l %d1,EXC_DREGS+0x8(%a6) # Save incr value
18659 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1
18662 mov.l %d1,EXC_DREGS+0xc(%a6) # Save incr value
18699 mov.l (%a6),%d0 # Get current a6
18702 mov.l %d1,(%a6) # Save incr value
18707 mov.b &mia7_flg,SPCOND_FLG(%a6) # set "special case" flag
18709 mov.l EXC_A7(%a6),%d0 # Get current a7
18712 mov.l %d1,EXC_A7(%a6) # Save incr value
18720 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0
18722 mov.l %d0,EXC_DREGS+0x8(%a6) # Save decr value
18727 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1
18729 mov.l %d0,EXC_DREGS+0xc(%a6) # Save decr value
18762 mov.l (%a6),%d0 # Get current a6
18764 mov.l %d0,(%a6) # Save decr value
18769 mov.b &mda7_flg,SPCOND_FLG(%a6) # set "special case" flag
18771 mov.l EXC_A7(%a6),%d0 # Get current a7
18773 mov.l %d0,EXC_A7(%a6) # Save decr value
18781 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18782 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18790 add.l EXC_DREGS+0x8(%a6),%a0 # a0 + d16
18794 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18795 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18803 add.l EXC_DREGS+0xc(%a6),%a0 # a1 + d16
18807 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18808 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18820 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18821 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18833 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18834 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18846 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18847 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18859 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18860 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18868 add.l (%a6),%a0 # a6 + d16
18872 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18873 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18881 add.l EXC_A7(%a6),%a0 # a7 + d16
18895 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18896 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18907 mov.l %d0,L_SCR1(%a6) # hold opword
18917 mov.l L_SCR1(%a6),%d2 # fetch opword
18940 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18941 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18954 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18955 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
18968 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18969 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18977 add.l EXC_EXTWPTR(%a6),%a0 # pc + d16