Lines Matching refs:cvmx_write_csr
257 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); in dwc3_octeon_config_power()
262 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); in dwc3_octeon_config_power()
267 cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); in dwc3_octeon_config_power()
274 cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); in dwc3_octeon_config_power()
280 cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); in dwc3_octeon_config_power()
363 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
368 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
380 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
390 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
427 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
435 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
449 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
457 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
462 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
480 cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64); in dwc3_octeon_set_endian_mode()
493 cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64); in dwc3_octeon_phy_reset()