Lines Matching refs:r4030_read_reg32
254 r4030_read_reg32(JAZZ_R4030_CONFIG)); in vdma_stats()
256 r4030_read_reg32(JAZZ_R4030_TRSTBL_BASE)); in vdma_stats()
258 r4030_read_reg32(JAZZ_R4030_TRSTBL_LIM)); in vdma_stats()
260 r4030_read_reg32(JAZZ_R4030_INV_ADDR)); in vdma_stats()
262 r4030_read_reg32(JAZZ_R4030_R_FAIL_ADDR)); in vdma_stats()
264 r4030_read_reg32(JAZZ_R4030_M_FAIL_ADDR)); in vdma_stats()
266 r4030_read_reg32(JAZZ_R4030_IRQ_SOURCE)); in vdma_stats()
268 r4030_read_reg32(JAZZ_R4030_I386_ERROR)); in vdma_stats()
272 (unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_MODE + in vdma_stats()
278 (unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + in vdma_stats()
300 status = r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5)); in vdma_enable()
310 r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + in vdma_enable()
318 r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + in vdma_enable()
332 r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + in vdma_disable()
340 (unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_MODE + in vdma_disable()
342 (unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_ADDR + in vdma_disable()
344 (unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_COUNT + in vdma_disable()
349 r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + in vdma_disable()
410 r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + in vdma_set_mode()
417 r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + in vdma_set_mode()
466 residual = r4030_read_reg32(JAZZ_R4030_CHNL_COUNT + (channel << 5)); in vdma_get_residue()
482 enable = r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5)); in vdma_get_enable()