Lines Matching refs:__raw_writel
63 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
64 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()
65 __raw_writel(TIMER_CCD, &tmrptr->ccdr); in txx9_clocksource_init()
66 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9_clocksource_init()
67 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); in txx9_clocksource_init()
68 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_clocksource_init()
83 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9tmr_stop_and_clear()
85 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()
96 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9tmr_set_state_periodic()
98 __raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> evt->shift, in txx9tmr_set_state_periodic()
100 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9tmr_set_state_periodic()
111 __raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr); in txx9tmr_set_state_oneshot()
122 __raw_writel(0, &tmrptr->itmr); in txx9tmr_set_state_shutdown()
133 __raw_writel(TIMER_CCD, &tmrptr->ccdr); in txx9tmr_tick_resume()
134 __raw_writel(0, &tmrptr->itmr); in txx9tmr_tick_resume()
147 __raw_writel(delta, &tmrptr->cpra); in txx9tmr_set_next_event()
148 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9tmr_set_next_event()
172 __raw_writel(0, &tmrptr->tisr); /* ack interrupt */ in txx9tmr_interrupt()
185 __raw_writel(TIMER_CCD, &tmrptr->ccdr); in txx9_clockevent_init()
186 __raw_writel(0, &tmrptr->itmr); in txx9_clockevent_init()
211 __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_tmr_init()
213 __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr); in txx9_tmr_init()
214 __raw_writel(0, &tmrptr->tisr); in txx9_tmr_init()
215 __raw_writel(0xffffffff, &tmrptr->cpra); in txx9_tmr_init()
216 __raw_writel(0, &tmrptr->itmr); in txx9_tmr_init()
217 __raw_writel(0, &tmrptr->ccdr); in txx9_tmr_init()
218 __raw_writel(0, &tmrptr->pgmr); in txx9_tmr_init()