Lines Matching refs:t1
178 1: PTR_L t1, VPEBOOTCFG_PC(v1)
181 jr t1
241 PTR_LA t1, 1f
242 jr.hb t1
272 sll t1, ta1, VPECONF0_XTC_SHIFT
273 or t0, t0, t1
310 li t1, COREBOOTCFG_SIZE
311 mul t0, t0, t1
312 PTR_LA t1, mips_cps_core_bootcfg
313 PTR_L t1, 0(t1)
314 PTR_ADDU v0, t0, t1
332 mfc0 t1, CP0_MVPCONF0
333 srl t1, t1, MVPCONF0_PVPE_SHIFT
334 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
335 addiu t1, t1, 1
338 clz t1, t1
340 subu t1, t2, t1
342 sll t1, t2, t1
343 addiu t1, t1, -1
347 and t9, t9, t1
351 li t1, VPEBOOTCFG_SIZE
352 mul v1, t9, t1
370 PTR_L t1, GCR_CPC_BASE_OFS(t3)
372 and t1, t1, t2
374 PTR_ADD t1, t1, t2
377 PTR_S ta2, CPC_CL_VC_RUN_OFS(t1)
381 PTR_S ta2, CPC_CL_VC_STOP_OFS(t1)
396 PTR_LA t1, 1f
397 jr.hb t1
399 1: mfc0 t1, CP0_MVPCONTROL
400 ori t1, t1, MVPCONTROL_VPC
401 mtc0 t1, CP0_MVPCONTROL
436 lw t1, VPEBOOTCFG_PC(t0)
437 mttc0 t1, CP0_TCRESTART
440 lw t1, VPEBOOTCFG_SP(t0)
441 mttgpr t1, sp
444 lw t1, VPEBOOTCFG_GP(t0)
445 mttgpr t1, gp
472 li t1, ~TCSTATUS_IXMT
473 and t0, t0, t1
492 mfc0 t1, CP0_MVPCONTROL
493 xori t1, t1, MVPCONTROL_VPC
494 mtc0 t1, CP0_MVPCONTROL
542 li t1, 2
543 sllv t0, t1, t0
546 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
547 xori t2, t1, 0x7
550 addiu t1, t1, 1
551 sllv t1, t3, t1
555 mul t1, t1, t0
556 mul t1, t1, t2
559 PTR_ADD a1, a0, t1
569 li t1, 2
570 sllv t0, t1, t0
573 _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
574 xori t2, t1, 0x7
577 addiu t1, t1, 1
578 sllv t1, t3, t1
582 mul t1, t1, t0
583 mul t1, t1, t2
586 PTR_ADDU a1, a0, t1
616 psstate t1
624 psstate t1