Lines Matching refs:i_format

433 	switch (insn.i_format.opcode) {  in isBranchInstr()
452 		switch (insn.i_format.rt) {  in isBranchInstr()
455 			if (NO_R6EMU && (insn.i_format.rs ||  in isBranchInstr()
456 			    insn.i_format.rt == bltzall_op))  in isBranchInstr()
468 			if ((long)regs->regs[insn.i_format.rs] < 0)  in isBranchInstr()
471 					(insn.i_format.simmediate << 2);  in isBranchInstr()
479 			if (NO_R6EMU && (insn.i_format.rs ||  in isBranchInstr()
480 			    insn.i_format.rt == bgezall_op))  in isBranchInstr()
492 			if ((long)regs->regs[insn.i_format.rs] >= 0)  in isBranchInstr()
495 					(insn.i_format.simmediate << 2);  in isBranchInstr()
524 		if (regs->regs[insn.i_format.rs] ==  in isBranchInstr()
525 		    regs->regs[insn.i_format.rt])  in isBranchInstr()
528 				(insn.i_format.simmediate << 2);  in isBranchInstr()
539 		if (regs->regs[insn.i_format.rs] !=  in isBranchInstr()
540 		    regs->regs[insn.i_format.rt])  in isBranchInstr()
543 				(insn.i_format.simmediate << 2);  in isBranchInstr()
550 		if (!insn.i_format.rt && NO_R6EMU)  in isBranchInstr()
567 		if (cpu_has_mips_r6 && insn.i_format.rt) {  in isBranchInstr()
568 			if ((insn.i_format.opcode == blez_op) &&  in isBranchInstr()
569 			    ((!insn.i_format.rs && insn.i_format.rt) ||  in isBranchInstr()
570 			     (insn.i_format.rs == insn.i_format.rt)))  in isBranchInstr()
578 		if ((long)regs->regs[insn.i_format.rs] <= 0)  in isBranchInstr()
581 				(insn.i_format.simmediate << 2);  in isBranchInstr()
588 		if (!insn.i_format.rt && NO_R6EMU)  in isBranchInstr()
605 		if (cpu_has_mips_r6 && insn.i_format.rt) {  in isBranchInstr()
606 			if ((insn.i_format.opcode == blez_op) &&  in isBranchInstr()
607 			    ((!insn.i_format.rs && insn.i_format.rt) ||  in isBranchInstr()
608 			     (insn.i_format.rs == insn.i_format.rt)))  in isBranchInstr()
617 		if ((long)regs->regs[insn.i_format.rs] > 0)  in isBranchInstr()
620 				(insn.i_format.simmediate << 2);  in isBranchInstr()
630 		if (insn.i_format.rt && !insn.i_format.rs)  in isBranchInstr()
638 		if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)  in isBranchInstr()
639 			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);  in isBranchInstr()
644 		if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)  in isBranchInstr()
645 			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);  in isBranchInstr()
650 		if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))  in isBranchInstr()
651 			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);  in isBranchInstr()
656 		if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))  in isBranchInstr()
657 			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);  in isBranchInstr()
692 		if (!insn.i_format.rs)  in isBranchInstr()
703 		    ((insn.i_format.rs == bc1eqz_op) ||  in isBranchInstr()
704 		     (insn.i_format.rs == bc1nez_op))) {  in isBranchInstr()
706 			fpr = &current->thread.fpu.fpr[insn.i_format.rt];  in isBranchInstr()
708 			switch (insn.i_format.rs) {  in isBranchInstr()
719 					(insn.i_format.simmediate << 2);  in isBranchInstr()
731 		if (insn.i_format.rs == bc_op) {  in isBranchInstr()
739 			bit = (insn.i_format.rt >> 2);  in isBranchInstr()
742 			switch (insn.i_format.rt & 3) {  in isBranchInstr()
748 						(insn.i_format.simmediate << 2);  in isBranchInstr()
759 						(insn.i_format.simmediate << 2);  in isBranchInstr()