Lines Matching defs:fec
392 typedef struct fec { struct
393 uint fec_addr_low; /* lower 32 bits of station address */ argument
394 ushort fec_addr_high; /* upper 16 bits of station address */ argument
396 uint fec_grp_hash_table_high; /* upper 32-bits of hash table */ argument
397 uint fec_grp_hash_table_low; /* lower 32-bits of hash table */ argument
398 uint fec_r_des_start; /* beginning of Rx descriptor ring */ argument
399 uint fec_x_des_start; /* beginning of Tx descriptor ring */ argument
400 uint fec_r_buff_size; /* Rx buffer size */ argument
402 uint fec_ecntrl; /* ethernet control register */ argument
403 uint fec_ievent; /* interrupt event register */ argument
404 uint fec_imask; /* interrupt mask register */ argument
405 uint fec_ivec; /* interrupt level and vector status */ argument
406 uint fec_r_des_active; /* Rx ring updated flag */ argument
407 uint fec_x_des_active; /* Tx ring updated flag */ argument
409 uint fec_mii_data; /* MII data register */ argument
410 uint fec_mii_speed; /* MII speed control register */ argument
412 uint fec_r_bound; /* end of RAM (read-only) */ argument
413 uint fec_r_fstart; /* Rx FIFO start address */ argument
415 uint fec_x_fstart; /* Tx FIFO start address */ argument
417 uint fec_fun_code; /* fec SDMA function code */ argument
419 uint fec_r_cntrl; /* Rx control register */ argument
420 uint fec_r_hash; /* Rx hash register */ argument
422 uint fec_x_cntrl; /* Tx control register */ argument
424 } fec_t; argument