Lines Matching refs:__MASK
64 #define __MASK(X) (1<<(X)) macro
66 #define __MASK(X) (1UL<<(X)) macro
70 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
71 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
72 #define MSR_S __MASK(MSR_S_LG) /* Secure state */
88 #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
89 #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */
90 #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
91 #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
92 #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
93 #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
94 #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
95 #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
96 #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
97 #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
98 #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
99 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
100 #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
101 #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
102 #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
103 #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
104 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
105 #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
106 #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
107 #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
108 #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
110 #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
112 #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
113 #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
115 #define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */
117 #define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
118 #define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
265 #define TEXASR_ABORT __MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */
266 #define TEXASR_SUSP __MASK(TEXASR_SU_LG) /* tx failed in suspended state */
267 #define TEXASR_HV __MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */
268 #define TEXASR_PR __MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */
269 #define TEXASR_FS __MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */
270 #define TEXASR_EXACT __MASK(TEXASR_EX_LG) /* TFIAR value is exact */
271 #define TEXASR_ROT __MASK(TEXASR_ROT_LG)
294 #define DAWRX_USER __MASK(0)
295 #define DAWRX_KERNEL __MASK(1)
296 #define DAWRX_HYP __MASK(2)
297 #define DAWRX_WTI __MASK(3)
298 #define DAWRX_WT __MASK(4)
299 #define DAWRX_DR __MASK(5)
300 #define DAWRX_DW __MASK(6)
304 #define DABRX_USER __MASK(0)
305 #define DABRX_KERNEL __MASK(1)
306 #define DABRX_HYP __MASK(2)
307 #define DABRX_BTI __MASK(3)
413 #define FSCR_PREFIX __MASK(FSCR_PREFIX_LG)
414 #define FSCR_SCV __MASK(FSCR_SCV_LG)
415 #define FSCR_TAR __MASK(FSCR_TAR_LG)
416 #define FSCR_EBB __MASK(FSCR_EBB_LG)
417 #define FSCR_DSCR __MASK(FSCR_DSCR_LG)
420 #define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
421 #define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
422 #define HFSCR_TAR __MASK(FSCR_TAR_LG)
423 #define HFSCR_EBB __MASK(FSCR_EBB_LG)
424 #define HFSCR_TM __MASK(FSCR_TM_LG)
425 #define HFSCR_PM __MASK(FSCR_PM_LG)
426 #define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
427 #define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
428 #define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
429 #define HFSCR_FP __MASK(FSCR_FP_LG)
483 #define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */
484 #define PCR_VSX_DIS (__MASK(63-1)) /* VSX disable (bit NA since POWER8) */
485 #define PCR_TM_DIS (__MASK(63-2)) /* Trans. memory disable (POWER8) */
486 #define PCR_MMA_DIS (__MASK(63-3)) /* Matrix-Multiply Accelerator */
591 #define HID0_POWER8_4LPARMODE __MASK(61)
592 #define HID0_POWER8_2LPARMODE __MASK(57)
593 #define HID0_POWER8_1TO2LPAR __MASK(52)
594 #define HID0_POWER8_1TO4LPAR __MASK(51)
595 #define HID0_POWER8_DYNLPARDIS __MASK(48)
598 #define HID0_POWER9_RADIX __MASK(63 - 8)