Lines Matching refs:r3
91 li r3,-1
126 rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
127 rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */
128 rlwinm r3,r3,0,1,31 /* Turn off the enable bit */
197 mtspr SPRN_L2CR,r3
208 oris r3,r3,0x0020
210 mtspr SPRN_L2CR,r3
217 10: mfspr r3,SPRN_L2CR
218 andis. r4,r3,0x0020
224 3: mfspr r3,SPRN_L2CR
225 rlwinm. r4,r3,0,31,31
228 11: rlwinm r3,r3,0,11,9 /* Turn off the L2I bit */
230 mtspr SPRN_L2CR,r3
238 oris r3,r3,0x8000
239 mtspr SPRN_L2CR,r3
244 mfspr r3,SPRN_MSSCR0
245 ori r3,r3,3
247 mtspr SPRN_MSSCR0,r3
267 li r3,0
269 mfspr r3,SPRN_L2CR
282 li r3,-1
302 rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
303 rlwinm r3,r3,0,22,20 /* Turn off the invalidate bit */
304 rlwinm r3,r3,0,2,31 /* Turn off the enable & PE bits */
305 rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
327 mtspr SPRN_L3CR,r3
330 oris r3,r3,L3CR_L3RES@h /* Set reserved bit 5 */
331 mtspr SPRN_L3CR,r3
333 oris r3,r3,L3CR_L3CLKEN@h /* Set clken */
334 mtspr SPRN_L3CR,r3
343 ori r3,r3,0x0400
345 mtspr SPRN_L3CR,r3
350 10: mfspr r3,SPRN_L3CR
351 andi. r4,r3,0x0400
355 rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
356 mtspr SPRN_L3CR,r3
369 oris r3,r3,(L3CR_L3E | L3CR_L3CLKEN)@h
370 mtspr SPRN_L3CR,r3
386 li r3,0
388 mfspr r3,SPRN_L3CR
411 li r3,0x4000 /* 512kB / 32B */
412 mtctr r3
413 lis r3,KERNELBASE@h
415 lwz r0,0(r3)
416 addi r3,r3,0x0020 /* Go to start of next cache line */
422 li r3,0x4000 /* 512kB / 32B */
423 mtctr r3
424 lis r3,KERNELBASE@h
426 dcbf 0,r3
427 addi r3,r3,0x0020 /* Go to start of next cache line */
432 mfspr r3,SPRN_HID0
433 rlwinm r3,r3,0,18,15
434 mtspr SPRN_HID0,r3
447 mfspr r3,SPRN_HID0
448 ori r3,r3, HID0_ICE|HID0_ICFI|HID0_DCE|HID0_DCI
451 mtspr SPRN_HID0,r3
452 xori r3,r3, HID0_ICFI|HID0_DCI
453 mtspr SPRN_HID0,r3