Lines Matching refs:r5
37 mulhwu r4,r4,r5
40 mullw r7,r10,r5
44 mullw r9,r3,r5
45 mulhwu r10,r3,r5
97 lwz r5,CPU_SPEC_SETUP(r4)
98 cmpwi 0,r5,0
99 add r5,r5,r3
101 mtctr r5
119 mfspr r5,SPRN_HID0
120 rlwinm r5,r5,0,27,25
122 mtspr SPRN_HID0,r5
129 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
131 or r4,r4,r5
147 mfspr r5,SPRN_HID0
148 ori r5,r5,HID0_BTIC
150 mtspr SPRN_HID0,r5
236 rlwinm r5, r3, 0, L1_CACHE_BYTES - 1
239 0: twnei r5, 0 /* WARN if r3 is not cache aligned */
244 li r5,4
254 dcbt r5,r4
263 dcbz r5,r3
301 subfic r6,r5,32
302 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
303 addi r7,r5,32 # could be xori, or addi with -32
309 sraw r3,r3,r5 # MSW = MSW >> count
315 subfic r6,r5,32
316 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
317 addi r7,r5,32 # could be xori, or addi with -32
321 slw r4,r4,r5 # LSW = LSW << count
327 subfic r6,r5,32
328 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
329 addi r7,r5,32 # could be xori, or addi with -32
333 srw r3,r3,r5 # MSW = MSW >> count
343 cmpw r3,r5
358 cmplw r3,r5