Lines Matching refs:r8
120 ld r8, 112+PPC_LR_STKOFF(r1)
132 mtsrr0 r8
153 ld r8,VCORE_LPCR(r5)
154 mtspr SPRN_LPCR,r8
539 addi r8, r5, VCORE_ENTRY_EXIT
540 21: lwarx r3, 0, r8
544 stwcx. r3, 0, r8
569 22: ld r8,VCORE_TB_OFFSET(r5)
570 cmpdi r8,0
572 std r8, VCORE_TB_OFFSET_APPL(r5)
574 add r8,r8,r6
575 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
581 addis r8,r8,0x100 /* if so, increment upper 40 bits */
582 mtspr SPRN_TBU40,r8
595 ld r8, VCORE_DPDES(r5)
597 mtspr SPRN_DPDES, r8
631 ld r8,VCPU_SPURR(r4)
633 mtspr SPRN_SPURR,r8
640 mfspr r8, SPRN_IAMR
644 std r8, STACK_SLOT_IAMR(r1)
736 ld r8, VCPU_TAR(r4)
738 mtspr SPRN_TAR, r8
740 ld r8, VCPU_EBBHR(r4)
742 mtspr SPRN_EBBHR, r8
746 ld r8, VCPU_WORT(r4)
750 mtspr SPRN_WORT, r8
755 ld r8, VCPU_TACR(r4)
759 mtspr SPRN_TACR, r8
766 ld r8, VCPU_SPRG3(r4)
770 mtspr SPRN_SPRG3, r8
812 ld r8,VCORE_LPCR(r5)
813 mtspr SPRN_LPCR,r8
819 ld r8,VCPU_DEC_EXPIRES(r4)
823 add r8,r8,r6
825 subf r3,r7,r8
846 1: ld r8,VCPU_SLB_E(r6)
848 slbmte r9,r8
917 ld r8, VCPU_GPR(R8)(r4)
1005 std r8, VCPU_GPR(R8)(r9)
1065 ld r8, VCPU_GPR(R8)(r9)
1156 1: slbmfee r8,r6
1157 andis. r0,r8,SLB_ESID_V@h
1159 add r8,r8,r6 /* put index in */
1161 std r8,VCPU_SLB_E(r7)
1175 ld r8,PACA_SLBSHADOWPTR(r13)
1179 LDX_BE r5, r8, r3
1181 LDX_BE r6, r8, r3
1185 1: addi r8,r8,16
1228 ld r8,VCPU_SPURR(r9)
1232 subf r6,r8,r6
1259 mfspr r8, SPRN_EBBHR
1260 std r8, VCPU_EBBHR(r9)
1264 mfspr r8, SPRN_WORT
1268 std r8, VCPU_WORT(r9)
1272 mfspr r8, SPRN_TACR
1276 std r8, VCPU_TACR(r9)
1295 ld r8, STACK_SLOT_IAMR(r1)
1296 mtspr SPRN_IAMR, r8
1309 mfspr r8, SPRN_DSCR
1311 std r8, VCPU_DSCR(r9)
1365 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1366 cmpdi r8, 0
1369 LWZX_BE r3, r8, r4
1371 STWX_BE r3, r8, r4
1380 lbz r4, LPPACA_PMCINUSE(r8)
1434 li r8,LPID_RSVD /* switch to reserved LPID */
1435 mtspr SPRN_LPID,r8
1444 mfspr r8, SPRN_VTB
1446 std r8, VCORE_VTB(r5)
1448 li r8, 0
1449 mtspr SPRN_DPDES, r8
1453 ld r8, VCORE_TB_OFFSET_APPL(r5)
1454 cmpdi r8,0
1459 subf r8,r8,r6
1460 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1466 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1467 mtspr SPRN_TBU40,r8
1493 19: lis r8,0x7fff /* MAX_INT@h */
1494 mtspr SPRN_HDEC,r8
1496 16: ld r8,KVM_HOST_LPCR(r4)
1497 mtspr SPRN_LPCR,r8
1651 ld r8, VCPU_XER(r9)
1653 mtxer r8
1662 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1673 lwz r8, 0(r10)
1677 stw r8, VCPU_LAST_INST(r9)
2086 lwz r8,VCORE_ENTRY_EXIT(r5)
2087 clrldi r8,r8,56
2093 cmpw r4,r8
2461 ori r8,r5,MSR_FP
2464 oris r8,r8,MSR_VEC@h
2469 oris r8,r8,MSR_VSX@h
2472 mtmsrd r8
2496 ori r8,r9,MSR_FP
2499 oris r8,r8,MSR_VEC@h
2504 oris r8,r8,MSR_VSX@h
2507 mtmsrd r8
2548 mfmsr r8
2550 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2551 mtmsrd r8
2553 rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */
2801 lwz r8, VCPU_PMC + 16(r4)
2807 mtspr SPRN_PMC5, r8
2813 ld r8, VCPU_SDAR(r4)
2817 mtspr SPRN_SDAR, r8
2833 lwz r8, VCPU_PMC + 28(r4)
2836 mtspr SPRN_SPMC2, r8
2864 lwz r8, HSTATE_PMC5(r13)
2870 mtspr SPRN_PMC5, r8
2882 ld r8, HSTATE_MMCR2(r13)
2884 mtspr SPRN_MMCR2, r8
2907 mr r8, r4
2941 cmpwi r8, 0 /* did they ask for PMU stuff to be saved? */
2947 mfspr r8, SPRN_SDAR
2963 std r8, VCPU_SDAR(r9)
2969 mfspr r8, SPRN_PMC6
2975 stw r8, VCPU_PMC + 20(r9)
2982 mfspr r8, SPRN_MMCRS
2985 std r8, VCPU_MMCRS(r9)
3030 ld r8, VCORE_TB_OFFSET_APPL(r5)
3035 subf r7, r8, r7 /* subtract current timebase offset */
3040 ld r8, TAS_SEQCOUNT(r5)
3041 cmpdi r8, 0
3042 addi r8, r8, 1
3043 std r8, TAS_SEQCOUNT(r5)
3058 addi r8, r8, 1
3059 std r8, TAS_SEQCOUNT(r5)