Lines Matching refs:C
27 #define C(x) PERF_COUNT_HW_CACHE_##x macro
34 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
39 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
40 [C(OP_READ)] = { 27, 0 },
41 [C(OP_WRITE)] = { 28, 0 },
42 [C(OP_PREFETCH)] = { 29, 0 },
44 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
45 [C(OP_READ)] = { 2, 60 },
46 [C(OP_WRITE)] = { -1, -1 },
47 [C(OP_PREFETCH)] = { 0, 0 },
55 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
56 [C(OP_READ)] = { 0, 0 },
57 [C(OP_WRITE)] = { 0, 0 },
58 [C(OP_PREFETCH)] = { 0, 0 },
66 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
67 [C(OP_READ)] = { 26, 66 },
68 [C(OP_WRITE)] = { -1, -1 },
69 [C(OP_PREFETCH)] = { -1, -1 },
71 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
72 [C(OP_READ)] = { 12, 15 },
73 [C(OP_WRITE)] = { -1, -1 },
74 [C(OP_PREFETCH)] = { -1, -1 },
76 [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
77 [C(OP_READ)] = { -1, -1 },
78 [C(OP_WRITE)] = { -1, -1 },
79 [C(OP_PREFETCH)] = { -1, -1 },