Lines Matching refs:C
168 #define C(x) PERF_COUNT_HW_CACHE_##x macro
175 static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
176 [ C(L1D) ] = {
177 [ C(OP_READ) ] = {
178 [ C(RESULT_ACCESS) ] = 0,
179 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
181 [ C(OP_WRITE) ] = {
182 [ C(RESULT_ACCESS) ] = 0,
183 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
185 [ C(OP_PREFETCH) ] = {
186 [ C(RESULT_ACCESS) ] = 0,
187 [ C(RESULT_MISS) ] = 0,
190 [ C(L1I) ] = {
191 [ C(OP_READ) ] = {
192 [ C(RESULT_ACCESS) ] = 0,
193 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
195 [ C(OP_WRITE) ] = {
196 [ C(RESULT_ACCESS) ] = 0,
197 [ C(RESULT_MISS) ] = -1,
199 [ C(OP_PREFETCH) ] = {
200 [ C(RESULT_ACCESS) ] = 0,
201 [ C(RESULT_MISS) ] = 0,
204 [ C(LL) ] = {
205 [ C(OP_READ) ] = {
206 [ C(RESULT_ACCESS) ] = 0,
207 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
209 [ C(OP_WRITE) ] = {
210 [ C(RESULT_ACCESS) ] = 0,
211 [ C(RESULT_MISS) ] = 0,
213 [ C(OP_PREFETCH) ] = {
214 [ C(RESULT_ACCESS) ] = 0,
215 [ C(RESULT_MISS) ] = 0,
218 [ C(DTLB) ] = {
219 [ C(OP_READ) ] = {
220 [ C(RESULT_ACCESS) ] = 0,
221 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
223 [ C(OP_WRITE) ] = {
224 [ C(RESULT_ACCESS) ] = -1,
225 [ C(RESULT_MISS) ] = -1,
227 [ C(OP_PREFETCH) ] = {
228 [ C(RESULT_ACCESS) ] = -1,
229 [ C(RESULT_MISS) ] = -1,
232 [ C(ITLB) ] = {
233 [ C(OP_READ) ] = {
234 [ C(RESULT_ACCESS) ] = 0,
235 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
237 [ C(OP_WRITE) ] = {
238 [ C(RESULT_ACCESS) ] = -1,
239 [ C(RESULT_MISS) ] = -1,
241 [ C(OP_PREFETCH) ] = {
242 [ C(RESULT_ACCESS) ] = -1,
243 [ C(RESULT_MISS) ] = -1,
246 [ C(BPU) ] = {
247 [ C(OP_READ) ] = {
248 [ C(RESULT_ACCESS) ] = 0,
249 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
251 [ C(OP_WRITE) ] = {
252 [ C(RESULT_ACCESS) ] = -1,
253 [ C(RESULT_MISS) ] = -1,
255 [ C(OP_PREFETCH) ] = {
256 [ C(RESULT_ACCESS) ] = -1,
257 [ C(RESULT_MISS) ] = -1,
260 [ C(NODE) ] = {
261 [ C(OP_READ) ] = {
262 [ C(RESULT_ACCESS) ] = -1,
263 [ C(RESULT_MISS) ] = -1,
265 [ C(OP_WRITE) ] = {
266 [ C(RESULT_ACCESS) ] = -1,
267 [ C(RESULT_MISS) ] = -1,
269 [ C(OP_PREFETCH) ] = {
270 [ C(RESULT_ACCESS) ] = -1,
271 [ C(RESULT_MISS) ] = -1,
276 #undef C