Lines Matching refs:C
320 #define C(x) PERF_COUNT_HW_CACHE_##x macro
327 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
328 [ C(L1D) ] = {
329 [ C(OP_READ) ] = {
330 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
331 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
333 [ C(OP_WRITE) ] = {
334 [ C(RESULT_ACCESS) ] = 0,
335 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
337 [ C(OP_PREFETCH) ] = {
338 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
339 [ C(RESULT_MISS) ] = 0,
342 [ C(L1I) ] = {
343 [ C(OP_READ) ] = {
344 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
345 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
347 [ C(OP_WRITE) ] = {
348 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
349 [ C(RESULT_MISS) ] = -1,
351 [ C(OP_PREFETCH) ] = {
352 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
353 [ C(RESULT_MISS) ] = 0,
356 [ C(LL) ] = {
357 [ C(OP_READ) ] = {
358 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
359 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
361 [ C(OP_WRITE) ] = {
362 [ C(RESULT_ACCESS) ] = 0,
363 [ C(RESULT_MISS) ] = 0,
365 [ C(OP_PREFETCH) ] = {
366 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
367 [ C(RESULT_MISS) ] = 0,
370 [ C(DTLB) ] = {
371 [ C(OP_READ) ] = {
372 [ C(RESULT_ACCESS) ] = 0,
373 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
375 [ C(OP_WRITE) ] = {
376 [ C(RESULT_ACCESS) ] = -1,
377 [ C(RESULT_MISS) ] = -1,
379 [ C(OP_PREFETCH) ] = {
380 [ C(RESULT_ACCESS) ] = -1,
381 [ C(RESULT_MISS) ] = -1,
384 [ C(ITLB) ] = {
385 [ C(OP_READ) ] = {
386 [ C(RESULT_ACCESS) ] = 0,
387 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
389 [ C(OP_WRITE) ] = {
390 [ C(RESULT_ACCESS) ] = -1,
391 [ C(RESULT_MISS) ] = -1,
393 [ C(OP_PREFETCH) ] = {
394 [ C(RESULT_ACCESS) ] = -1,
395 [ C(RESULT_MISS) ] = -1,
398 [ C(BPU) ] = {
399 [ C(OP_READ) ] = {
400 [ C(RESULT_ACCESS) ] = PM_BR_CMPL,
401 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
403 [ C(OP_WRITE) ] = {
404 [ C(RESULT_ACCESS) ] = -1,
405 [ C(RESULT_MISS) ] = -1,
407 [ C(OP_PREFETCH) ] = {
408 [ C(RESULT_ACCESS) ] = -1,
409 [ C(RESULT_MISS) ] = -1,
412 [ C(NODE) ] = {
413 [ C(OP_READ) ] = {
414 [ C(RESULT_ACCESS) ] = -1,
415 [ C(RESULT_MISS) ] = -1,
417 [ C(OP_WRITE) ] = {
418 [ C(RESULT_ACCESS) ] = -1,
419 [ C(RESULT_MISS) ] = -1,
421 [ C(OP_PREFETCH) ] = {
422 [ C(RESULT_ACCESS) ] = -1,
423 [ C(RESULT_MISS) ] = -1,
428 #undef C